Cross Reference: /art/compiler/optimizing/code_generator

Lines Matching refs:ip0
1208   //      ip0       : VIXL core temp.
4475       assembler.JumpTo(ManagedRegister(arm64::X0), offset, ManagedRegister(arm64::IP0));
5805       DCHECK(temps.IsAvailable(ip0));
5807       temps.Exclude(ip0, ip1);
5900   DCHECK(temps.IsAvailable(ip0));
5902   temps.Exclude(ip0, ip1);
6002   DCHECK(temps.IsAvailable(ip0));
6004   temps.Exclude(ip0, ip1);
6180   __ Ldr(ip0.W(), lock_word);
6184   __ Tbnz(ip0.W(), LockWord::kReadBarrierStateShift, slow_path);
6200   __ Add(base_reg, base_reg, Operand(ip0, LSR, 32));
6209   DCHECK_EQ(ip0.GetCode(), 16u);
6211       Thread::ReadBarrierMarkEntryPointsOffset<kArm64PointerSize>(ip0.GetCode());
6229       temps.Exclude(ip0, ip1);
6249         __ Ldr(ip0.W(), ldr_address);         // Load the LDR (immediate) unsigned offset.
6251         __ Ubfx(ip0.W(), ip0.W(), 10, 12);    // Extract the offset.
6252         __ Ldr(ip0.W(), MemOperand(base_reg, ip0, LSL, 2));   // Load the reference.
6257         __ Ldar(ip0.W(), MemOperand(base_reg));
6270       temps.Exclude(ip0, ip1);
6279       __ Ldr(ip0.W(), ldr_address);         // Load the LDR (register) unsigned offset.
6281       __ Ubfx(ip0, ip0, 16, 6);             // Extract the index register, plus 32 (bit 21 is set).
6282       __ Bfi(ip1, ip0, 3, 6);               // Insert ip0 to the entrypoint address to create
6284       __ Mov(ip0, base_reg);                // Move the base register to ip0.
6299       temps.Exclude(ip0, ip1);
6303       __ Ldr(ip0.W(), lock_word);
6304       __ Tbz(ip0.W(), LockWord::kMarkBitStateShift, &not_marked);
6308       __ Tst(ip0.W(), Operand(ip0.W(), LSL, 1));
6314       __ Mov(ip0.W(), root_reg);
6317       __ Lsl(root_reg, ip0.W(), LockWord::kForwardingAddressShift);
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