Lines Matching refs:out_reg
467 vixl32::Register out_reg = OutputRegister(invoke);
475 __ Vmov(out_reg, temp1);
478 __ Cmp(out_reg, 0);
483 // If input is a negative tie, change rounding direction to positive infinity, out_reg += 1.
495 __ add(eq, out_reg, out_reg, 1);
