Lines Matching refs:PMU_BASE
30 regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b);
33 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)
38 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
41 regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b);
143 val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ);
149 mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val);
151 while ((mmio_read_32(PMU_BASE +
156 mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST),
165 regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b);
173 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) &
181 regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b);
183 while (!(mmio_read_32(PMU_BASE +
188 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
210 regs_updata_bit_set(PMU_BASE + PMU_WKUP_CFG2, pmu_cluster_l_wkup_en);
211 regs_updata_bit_set(PMU_BASE + PMU_WKUP_CFG2, pmu_cluster_b_wkup_en);
212 regs_updata_bit_clr(PMU_BASE + PMU_WKUP_CFG2, pmu_gpio_wkup_en);
214 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(2));
215 mmio_write_32(PMU_BASE + PMU_PLLRST_CNT, CYCL_24M_CNT_US(100));
216 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(2));
217 mmio_write_32(PMU_BASE + PMU_PWRMD_CORE, pwrmd_core);
218 mmio_write_32(PMU_BASE + PMU_PWRMD_COM, pwrmd_com);
226 regs_updata_bit_set(PMU_BASE + PMU_PWRMD_CORE, pmu_mdcr_global_int_dis);
227 regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_glbl_int_dis_b);
369 mmio_read_32(PMU_BASE + PMU_PWRDN_ST));
