Lines Matching refs:PMU_BASE
77 mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req);
80 bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id;
81 bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id;
88 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST),
91 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK),
324 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);
397 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
404 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
412 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
419 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) &
428 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
430 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
435 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
441 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
476 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
480 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0);
491 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
513 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
524 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
551 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);
561 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);
686 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
710 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE);
779 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30));
780 mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(30));
783 mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3));
786 mmio_write_32(PMU_BASE + PMU_TIMEOUT_CNT, 0x5dc0);
791 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3));
792 mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(1));
793 mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(1));
794 mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(1));
805 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(5));
806 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_US(1));
815 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_US(1));
816 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_US(1));
817 mmio_write_32(PMU_BASE + PMU_GPU_PWRDN_CNT, CYCL_24M_CNT_US(1));
818 mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1));
835 mmio_write_32(PMU_BASE + PMU_CCI500_CON,
840 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
872 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN));
873 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
875 mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW);
882 mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
887 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
1356 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
1364 while ((mmio_read_32(PMU_BASE +
1369 mmio_read_32(PMU_BASE + PMU_ADB400_ST));
1373 mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
1430 mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff);
1431 mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00);
1437 mmio_write_32(PMU_BASE + PMU_CCI500_CON,
1442 mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON,
1445 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
1457 while ((mmio_read_32(PMU_BASE +
1462 mmio_read_32(PMU_BASE + PMU_ADB400_ST));
1585 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE);
1598 mmio_read_32(PMU_BASE + PMU_PWRDN_ST));
