Lines Matching refs:BIT31
197 #define EnableIMRInt BIT31
199 #define EnableSMMInt BIT31
214 #define IMR_LOCK BIT31
380 #define B_QNC_LPC_SMBUS_BASE_EN (BIT31)
508 #define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI
521 #define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable
554 #define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31)
694 #define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable
750 #define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers.
