Lines Matching refs:tCL
393 uint8_t TCL, WL;
415 TCL = mrc_params->params.tCL; // CAS latency in clocks
416 TRP = TCL; // Per CAT MRC
417 TRCD = TCL; // Per CAT MRC
430 Dtr0.field.tCL = TCL - 5; //Convert from TCL (DRAM clocks) to VLV indx
452 Dtr3.field.tRWSR = TCL - 5 + 1;
457 Dtr3.field.tRWSR = TCL - 5 + 1;
473 Dtr4.field.RDODTSTRT = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2; //Convert from WL (DRAM clocks) to VLV indx
474 Dtr4.field.RDODTSTOP = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2;
506 tCAS = mrc_params->params.tCL;
1036 mrs0Command.field.casLatency = DTR0reg.field.tCL + 1;
