Lines Matching refs:BIT0
87 #define B_PCH_LPSS_DMAC_BAR_MS BIT0 // Message Space
94 #define B_PCH_LPSS_DMAC_BAR1_MS BIT0 // Message Space
122 #define B_PCH_LPSS_DMAC_PCS_PS (BIT1 | BIT0) // Power State
172 #define B_PCH_LPSS_I2C_BAR_MS BIT0 // Message Space
179 #define B_PCH_LPSS_I2C_BAR1_MS BIT0 // Message Space
207 #define B_PCH_LPSS_I2C_PCS_PS (BIT1 | BIT0) // Power State
218 #define B_PCH_LPSS_I2C_MEM_RESETS_APB BIT0 // APB Domain Reset
259 #define B_PCH_LPSS_PWM_BAR_MS BIT0 // Message Space
266 #define B_PCH_LPSS_PWM_BAR1_MS BIT0 // Message Space
294 #define B_PCH_LPSS_PWM_PCS_PS (BIT1 | BIT0) // Power State
305 #define B_PCH_LPSS_PWM_MEM_RESETS_APB BIT0 // APB Domain Reset
346 #define B_PCH_LPSS_HSUART_BAR_MS BIT0 // Message Space
353 #define B_PCH_LPSS_HSUART_BAR1_MS BIT0 // Message Space
381 #define B_PCH_LPSS_HSUART_PCS_PS (BIT1 | BIT0) // Power State
394 #define B_PCH_LPSS_HSUART_MEM_PCP_CLKEN BIT0 // Clock Enable
398 #define B_PCH_LPSS_HSUART_MEM_RESETS_APB BIT0 // APB Domain Reset
438 #define B_PCH_LPSS_SPI_BAR_MS BIT0 // Message Space
445 #define B_PCH_LPSS_SPI_BAR1_MS BIT0 // Message Space
473 #define B_PCH_LPSS_SPI_PCS_PS (BIT1 | BIT0) // Power State
486 #define B_PCH_LPSS_SPI_MEM_PCP_CLKEN BIT0 // Clock Enable
490 #define B_PCH_LPSS_SPI_MEM_RESETS_APB BIT0 // APB Domain Reset
