Lines Matching refs:BIT0
85 #define B_PCH_LPC_COMMAND_IOSE BIT0 // I/O Space Enable
142 #define B_PCH_LPC_ACPI_BASE_MEMI BIT0 // Memory Space Indication
149 #define B_PCH_LPC_PMC_BASE_MEMI BIT0 // Memory Space Indication
154 #define B_PCH_LPC_GPIO_BASE_MEMI BIT0 // Memory Space Indication
161 #define B_PCH_LPC_IO_BASE_MEMI BIT0 // Memory Space Indication
168 #define B_PCH_LPC_ILB_BASE_MEMI BIT0 // Memory Space Indication
175 #define B_PCH_LPC_SPI_BASE_MEMI BIT0 // Memory Space Indicator
182 #define B_PCH_LPC_MPHY_BASE_MEMI BIT0 // Memory Space Indicator
189 #define B_PCH_LPC_PUNIT_BASE_MEMI BIT0 // Memory Space Indicator
192 #define B_PCH_LPC_UART_CTRL_COM1_EN BIT0 // COM1 Enable
208 #define B_PCH_LPC_FWH_BIOS_DEC_E40 BIT0 // 40-4F Enable
227 #define B_PCH_LPC_RCBA_EN BIT0 // Enable Bit
244 #define B_PCH_LPC_CGC_PRITCG BIT0 // IOSF-PRI Trunk Clock Gating (Request) Disable
250 #define B_PCH_ILB_ACPI_CNT_SCI_IRQ_SEL (BIT2 | BIT1 | BIT0) // SCI IRQ Select
252 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_10 BIT0 // IRQ10
255 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_21 (BIT2 | BIT0) // IRQ21 (Only if APIC enabled)
257 #define V_PCH_ILB_ACPI_CNT_SCI_IRQ_23 (BIT2 | BIT1 | BIT0) // IRQ23 (Only if APIC enabled)
263 #define B_PCH_ILB_MC_AME BIT0 // Alternate Access Mode Enable
301 #define B_PCH_ILB_ULKMC_60REN BIT0 // SMI on Port 60 Reads Enable
318 #define B_PCH_ILB_BIOS_CNTL_WP BIT0 // Write Protect
383 #define B_PCH_ILB_DXXIR_IAR_MASK (BIT2 | BIT1 | BIT0) // INTA Mask
385 #define V_PCH_ILB_DXXIR_IAR_PIRQB BIT0 // INTA Mapping to IRQ B
387 #define V_PCH_ILB_DXXIR_IAR_PIRQD (BIT1 | BIT0) // INTA Mapping to IRQ D
389 #define V_PCH_ILB_DXXIR_IAR_PIRQF (BIT2 | BIT0) // INTA Mapping to IRQ F
391 #define V_PCH_ILB_DXXIR_IAR_PIRQH (BIT2 | BIT1 | BIT0) // INTA Mapping to IRQ H
399 #define B_PCH_ILB_RTC_CONF_LCMOS_LOCK BIT0 // Lower 128 Byte Lock
402 #define B_PCH_ILB_RTM_RTM1 (BIT2 | BIT1 | BIT0)
406 #define B_PCH_ILB_BCS_SMIWPST BIT0 // SMI WPD Status
410 #define B_PCH_ILB_LE_IRQ1C BIT0 // IRQ1 Cause
419 #define B_PCH_ILB_RTCC_FEN BIT0 // Enable the Fast Oscillator Bypass Mode
434 #define B_PCH_ILB_DEF1_DSAEOI BIT0 // 8259 Disable_Slave_AEOI
446 #define B_PCH_ILB_GNMI_GNMIS BIT0 // GPIO NMI Status
453 #define B_PCH_ILB_LPCC_LPCCLK0EN BIT0 // Clock 0 Enable
474 #define B_PCH_ACPI_PM1_STS_TMROF BIT0 // Timer Overflow Status
492 #define B_PCH_ACPI_PM1_EN_TMROF BIT0 // Timer Overflow Interrupt Enable Bit
509 #define B_PCH_ACPI_PM1_CNT_SCI_EN BIT0 // SCI Enable
565 #define B_PCH_SMI_EN_GBL_SMI BIT0 // Global SMI Enable
630 #define B_PCH_UPRWC_WR_EN_SMI_EN BIT0 // Write Enable SMI Enable
637 #define B_PCH_ACPI_GPE_CNTL_PCIE0_SCI_EN BIT0
640 #define B_PCH_ACPI_PM2_CNT_ARB_DIS BIT0 // Scratchpad Bit
679 #define B_PCH_PMC_PM_CFG_TIMING_T581 (BIT1 | BIT0) // Timing t581
724 #define B_PCH_PMC_GEN_PMCON_AFTERG3_EN BIT0 // After G3 State Enable
731 #define B_PCH_PMC_GEN_PMCON_PER_SMI_SEL (BIT1 | BIT0) // Period SMI Select
740 #define B_PCH_PMC_SEC_STS_SEC (BIT3 | BIT2 | BIT1 | BIT0) // SEC Exclusion Cause
743 #define B_PCH_PMC_CRID_RID_SEL (BIT1 | BIT0) // Revision ID Select
778 #define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC0 BIT0 // LPSS1 DMA Disable
783 #define B_PCH_PMC_FUNC_DIS2_SMBUS BIT0 // SMBus Disable
795 #define B_PCH_PMC_GPI_ROUT_0 (BIT1 | BIT0)
814 #define B_PCH_PMC_PCC0_CLK_CTL (BIT1 | BIT0) // Clock Gating
818 #define B_PCH_PMC_PCC1_CLK_CTL (BIT1 | BIT0) // Clock Gating
822 #define B_PCH_PMC_PCC2_CLK_CTL (BIT1 | BIT0) // Clock Gating
826 #define B_PCH_PMC_PCC3_CLK_CTL (BIT1 | BIT0) // Clock Gating
830 #define B_PCH_PMC_PCC4_CLK_CTL (BIT1 | BIT0) // Clock Gating
834 #define B_PCH_PMC_PCC5_CLK_CTL (BIT1 | BIT0) // Clock Gating
900 #define B_PCH_PMC_D3_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0
906 #define B_PCH_PMC_D3_STS_1_SMB BIT0 // SMBus
937 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F0 BIT0 // LPSS 0 Function 0
943 #define B_PCH_PMC_D3_STDBY_STS_1_SMB BIT0 // SMBus
1031 #define B_PCH_NMI_SC_TIM_CNT2_EN BIT0 // Timer Counter 2 Enable
1068 #define B_PCH_RTC_REGISTERA_RS (BIT3 | BIT2 | BIT1 | BIT0) // Rate Select
1094 #define B_PCH_RTC_REGISTERB_DSE BIT0 // Daylight Savings Enable (Not Implemented)
1101 #define B_PCH_RTC_REGISTERC_RESERVED (BIT3 | BIT2 | BIT1 | BIT0)
1121 #define B_PCH_PORT92_INIT_NOW BIT0 // Init Now
1176 #define B_PCH_PCH_HPET_GCFG_EN BIT0 // Overall Enable
1181 #define B_PCH_PCH_HPET_GIS_T0 BIT0 // Timer 0 Status
