Lines Matching refs:BIT3
82 #define B_PCH_LPC_COMMAND_SCE BIT3 // Special Cycle Enable
98 #define B_PCH_LPC_DEV_STS_INT_STS BIT3 // Interrupt Status
146 #define B_PCH_LPC_PMC_BASE_PREF BIT3 // Prefetchable
158 #define B_PCH_LPC_IO_BASE_PREF BIT3 // Prefetchable
165 #define B_PCH_LPC_ILB_BASE_PREF BIT3 // Prefetchable
172 #define B_PCH_LPC_SPI_BASE_PREF BIT3 // Prefetchable
179 #define B_PCH_LPC_MPHY_BASE_PREF BIT3 // Prefetchable
186 #define B_PCH_LPC_PUNIT_BASE_PREF BIT3 // Prefetchable
205 #define B_PCH_LPC_FWH_BIOS_DEC_E70 BIT3 // 70-7F Enable
260 #define B_PCH_ILB_MC_DRTC BIT3 // Disable RTC
298 #define B_PCH_ILB_ULKMC_64WEN BIT3 // SMI on Port 64 Writes Enable
416 #define B_PCH_ILB_RTCC_RTCB1 BIT3 // RTC Bias Resistor 1, Adds 60 Kohm
431 #define B_PCH_ILB_DEF1_LMOO BIT3 // 8259 L2L0_Match_On_OCW2
443 #define B_PCH_ILB_GNMI_NMINS BIT3 // NMI NOW Status
450 #define B_PCH_ILB_LPCC_LPCCLK_FORCE_OFF BIT3
457 #define B_PCH_ILB_IRQE_UARTIRQEN_IRQ3 BIT3 // UART IRQ3 Enable
472 #define B_PCH_ACPI_PM1_STS_WAK_PCIE2 BIT3 // PCI Express 2 Wake Status
490 #define B_PCH_ACPI_PM1_WAK_DIS_PCIE2 BIT3 // PCI Express 2 Disable
634 #define B_PCH_ACPI_GPE_CNTL_PCIE3_SCI_EN BIT3
648 #define B_PCH_TCO_STS_TIMEOUT BIT3 // Timeout
678 #define B_PCH_PMC_PM_CFG_SX_ENT_TO_EN BIT3 // S1 / 3 / 4 / 5 Entry Timeout Enable
722 #define B_PCH_PMC_GEN_PMCON_SLP_S4_ASE BIT3 // SLP_S4# Assertion Scretch Enable
740 #define B_PCH_PMC_SEC_STS_SEC (BIT3 | BIT2 | BIT1 | BIT0) // SEC Exclusion Cause
775 #define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC3 BIT3 // LPSS1 HS-UART #1 Disable
796 #define B_PCH_PMC_GPI_ROUT_1 (BIT3 | BIT2)
897 #define B_PCH_PMC_D3_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3
903 #define B_PCH_PMC_D3_STS_1_DFX BIT3 // DFX
934 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F3 BIT3 // LPSS 0 Function 3
940 #define B_PCH_PMC_D3_STDBY_STS_1_DFX BIT3 // DFX
1028 #define B_PCH_NMI_SC_IOCHK_NMI_EN BIT3 // IOCHK NMI Enable
1068 #define B_PCH_RTC_REGISTERA_RS (BIT3 | BIT2 | BIT1 | BIT0) // Rate Select
1091 #define B_PCH_RTC_REGISTERB_SQWE BIT3 // Square Wave Enable (Not implemented)
1101 #define B_PCH_RTC_REGISTERC_RESERVED (BIT3 | BIT2 | BIT1 | BIT0)
1132 #define B_PCH_RST_CNT_FULL_RST BIT3
1203 #define B_PCH_PCH_HPET_TXC_TYP BIT3 // Timer Type
