Lines Matching refs:BIT7
78 #define B_PCH_LPC_COMMAND_WCC BIT7 // Wait Cycle Control
95 #define B_PCH_LPC_DEV_STS_FB2B BIT7 // Fast Back to Back Capable
129 #define B_PCH_LPC_HEADTYP_MFD BIT7 // Multi-function Device
203 #define B_PCH_LPC_FWH_BIOS_DEC_LFE BIT7 // Legacy F Segment Enable
276 #define B_PCH_ILB_PIRQX_ROUT_IRQEN BIT7 // Interrupt Routing Enable
291 #define B_PCH_ILB_SERIRQ_CNT_SIRQMD BIT7 // Mode
456 #define B_PCH_ILB_IRQE_IRQ4TO7EN (BIT7 | BIT6 | BIT5 | BIT4) // IRQ4 - IRQ7 Enable
559 #define B_PCH_SMI_EN_BIOS_RLS BIT7 // BIOS RLS
670 #define B_PCH_PMC_PRSTS_SEC_GBLRST_STS BIT7 // SEC Global Reset Status
712 #define B_PCH_PMC_GEN_PMCON_SWSMI_RTSL (BIT7 | BIT6) // SWSMI Rate Select
771 #define B_PCH_PMC_FUNC_DIS_LPSS1_FUNC7 BIT7 // LPSS1 Spare #2 Disable
798 #define B_PCH_PMC_GPI_ROUT_3 (BIT7 | BIT6)
863 #define B_PCH_PMC_PSS_PG_STS_DFX BIT7 // DFX
893 #define B_PCH_PMC_D3_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
930 #define B_PCH_PMC_D3_STDBY_STS_0_LPSS0F7 BIT7 // LPSS 0 Function 7
1024 #define B_PCH_NMI_SC_SERR_NMI_STS BIT7 // SERR# NMI Status
1034 #define B_PCH_NMI_EN_NMI_EN BIT7 // NMI Enable, must preserve this bit first before writing to IO port 0x70
1060 #define B_PCH_RTC_REGISTERA_UIP BIT7 // Update In Progress
1087 #define B_PCH_RTC_REGISTERB_SET BIT7 // Update Cycle Inhibit 1: Stop auto update, begin set value; 0: Update cycle occurs
1097 #define B_PCH_RTC_REGISTERC_IRQF BIT7 // Interrupt Request Flag
1104 #define B_PCH_RTC_REGISTERD_VRT BIT7 // Valid RAM and Time Bit
