Lines Matching refs:resultId
121 void disassembleInstruction(Id resultId, Id typeId, Op opCode, int numOperands);
204 Id resultId = 0;
206 resultId = stream[word++];
210 idInstruction[resultId] = instructionStart;
213 outputResultId(resultId);
218 disassembleInstruction(resultId, typeId, opCode, numOperands);
337 void SpirvStream::disassembleInstruction(Id resultId, Id /*typeId*/, Op opCode, int numOperands)
351 idDescriptor[resultId] = (const char*)(&stream[word]);
354 if (resultId != 0 && idDescriptor[resultId].size() == 0) {
358 case 8: idDescriptor[resultId] = "int8_t"; break;
359 case 16: idDescriptor[resultId] = "int16_t"; break;
361 case 32: idDescriptor[resultId] = "int"; break;
362 case 64: idDescriptor[resultId] = "int64_t"; break;
367 case 16: idDescriptor[resultId] = "float16_t"; break;
369 case 32: idDescriptor[resultId] = "float"; break;
370 case 64: idDescriptor[resultId] = "float64_t"; break;
374 idDescriptor[resultId] = "bool";
377 idDescriptor[resultId] = "struct";
380 idDescriptor[resultId] = "ptr";
384 idDescriptor[resultId].append(idDescriptor[stream[word]].begin(), idDescriptor[stream[word]].begin() + 1);
386 idDescriptor[resultId].append("8");
389 idDescriptor[resultId].append("16");
392 idDescriptor[resultId].append("64");
395 idDescriptor[resultId].append("vec");
397 case 2: idDescriptor[resultId].append("2"); break;
398 case 3: idDescriptor[resultId].append("3"); break;
399 case 4: idDescriptor[resultId].append("4"); break;
400 case 8: idDescriptor[resultId].append("8"); break;
401 case 16: idDescriptor[resultId].append("16"); break;
402 case 32: idDescriptor[resultId].append("32"); break;
