Lines Matching refs:ps_ctl_op
2724 ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
2725 ps_ctl_op->u4_error_code = 0;
2739 ps_ctl_op->u4_error_code = 0;
2775 ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
2777 ps_ctl_op->u4_error_code = 0;
2784 ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
2785 ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
2804 ps_ctl_op->u4_pic_ht = pic_wd;
2805 ps_ctl_op->u4_pic_wd = pic_ht;
2819 ps_ctl_op->u4_num_disp_bufs = 1;
2827 ps_ctl_op->u4_num_disp_bufs =
2834 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
2837 ps_ctl_op->u4_num_disp_bufs +=
2842 ps_ctl_op->u4_num_disp_bufs = 32;
2844 ps_ctl_op->u4_num_disp_bufs = MAX(
2845 ps_ctl_op->u4_num_disp_bufs, 6);
2846 ps_ctl_op->u4_num_disp_bufs = MIN(
2847 ps_ctl_op->u4_num_disp_bufs, 32);
2850 ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
2852 ps_ctl_op->u4_frame_rate = 0; //make it proper
2853 ps_ctl_op->u4_bit_rate = 0; //make it proper
2854 ps_ctl_op->e_content_type = ps_dec->i4_content_type;
2855 ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
2856 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
2860 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2864 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2868 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2873 ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2879 ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
2883 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
2885 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
2891 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
2892 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
2894 ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
2899 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
2901 ps_ctl_op->u4_min_out_buf_size[1] =
2902 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2906 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
2908 ps_ctl_op->u4_min_out_buf_size[1] =
2909 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2914 ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
2915 ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
2917 ps_ctl_op->u4_min_out_buf_size[2] = 0;
2920 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
2951 ivd_ctl_getbufinfo_op_t *ps_ctl_op =
2956 ps_ctl_op->u4_error_code = 0;
2960 ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
2963 ps_ctl_op->u4_num_disp_bufs = 1;
2986 for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
2988 ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
2994 ps_ctl_op->u4_num_disp_bufs = 1;
3002 ps_ctl_op->u4_num_disp_bufs =
3009 ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3012 ps_ctl_op->u4_num_disp_bufs +=
3018 ps_ctl_op->u4_num_disp_bufs = 32;
3022 ps_ctl_op->u4_num_disp_bufs = MAX(
3023 ps_ctl_op->u4_num_disp_bufs, 6);
3024 ps_ctl_op->u4_num_disp_bufs = MIN(
3025 ps_ctl_op->u4_num_disp_bufs, 32);
3028 ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3032 for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3034 ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3037 ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3070 ivd_ctl_set_config_op_t *ps_ctl_op =
3077 ps_ctl_op->u4_error_code = 0;
3081 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3104 ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3105 ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3115 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3124 ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3160 ivd_ctl_set_config_op_t *ps_ctl_op =
3171 ps_ctl_op->u4_error_code = 0;
3235 ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3237 ps_ctl_op->u4_error_code = 0;
3249 ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3278 ivd_ctl_set_config_op_t *ps_ctl_op;
3289 ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3290 ps_ctl_op->u4_error_code = 0;
