Lines Matching refs:gb_tile_mode
1072 static void si_gb_tile_mode(uint32_t gb_tile_mode,
1081 switch (SI__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) {
1104 switch (SI__GB_TILE_MODE__NUM_BANKS(gb_tile_mode)) {
1121 switch (SI__GB_TILE_MODE__MACRO_TILE_ASPECT(gb_tile_mode)) {
1138 switch (SI__GB_TILE_MODE__BANK_WIDTH(gb_tile_mode)) {
1155 switch (SI__GB_TILE_MODE__BANK_HEIGHT(gb_tile_mode)) {
1172 switch (SI__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) {
1290 uint32_t gb_tile_mode;
1347 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode];
1348 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split);
1398 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode];
1399 si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_split);
1706 uint32_t gb_tile_mode;
1710 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1711 si_gb_tile_mode(gb_tile_mode, &num_pipes, &num_banks, NULL, NULL, NULL, NULL);
1867 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode];
1874 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(gb_tile_mode)) {
1900 switch (CIK__GB_TILE_MODE__TILE_SPLIT(gb_tile_mode)) {
1924 switch (CIK__GB_TILE_MODE__SAMPLE_SPLIT(gb_tile_mode)) {
