Lines Matching refs:dual
1376 VSWP D12,D13 @ dual issued with prev. instruction
1378 VSWP D14,D15 @ dual issued with prev. instruction
1383 VREV64.S32 Q9 ,Q9 @rev e[k] k-> 4-7 R1, dual issued with prev. instruction
1386 VSWP D18,D19 @ dual issued with prev. instruction
1388 VREV64.S32 Q13,Q13 @rev e[k] k-> 4-7 R2, dual issued with prev. instruction
1397 VREV64.S32 D5,D5 @rev ee[k] 4-7 R1, dual issued with prev. instruction
1401 VREV64.S32 D9,D9 @rev ee[k] 4-7 R2, dual issued with prev. instruction
1421 VSWP D7,D10 @ dual issued with prev. instruction
1436 VSWP D14,D15 @2G0 2G1 2G2 2G3 -> 2G2 2G3 2G0 2G1, dual issued with prev. instruction
1443 VSHRN.S32 D9,Q6,#SHIFT @NARROW R2, dual issued in 2nd cycle
1446 VSWP D16,D17 @dual issued with prev. instr.
1471 VSWP D14,D15 @ dual issued with prev. instruction
1495 VPADD.S32 D25,D4,D5 @ dual issued with prev. instruction in 2nd cycle
1498 VADD.S32 Q12,Q12,Q14 @Round by RADD R2, dual issued with prev. instruction in 2nd cycle
1505 VADD.S32 D11,D12,D13 @g_ai2_ihevc_trans_16[1][k]*o[0][k]+g_ai2_ihevc_trans_16[0][7-k]*o[0][7-k] R2, dual issued with prev. instr.
1509 VADD.S32 D10,D4,D5 @g_ai2_ihevc_trans_16[1][k]*o[0][k]+g_ai2_ihevc_trans_16[0][7-k]*o[0][7-k] R1, dual issued with prev. instr.
1529 VADD.S32 D26,D24,D25 @ dual issued with prev. instr.
1543 VPADD.S32 D17,D12,D13 @ dual issued with prev. instr. in 2nd cycle
1560 VADD.S32 D11,D12,D13 @ dual issued with prev. instr.
1573 VADD.S32 D19,D16,D17 @ dual issued with prev. instr.
