Lines Matching defs:TReg
112 unsigned TReg, FReg;
113 // Latencies from Cond+Branch, TReg, and FReg to DstReg.
117 : PHI(phi), TReg(0), FReg(0), CondCycles(0), TCycles(0), FCycles(0) {}
415 PI.TReg = PI.PHI->getOperand(i).getReg();
419 assert(TargetRegisterInfo::isVirtualRegister(PI.TReg) && "Bad PHI");
423 if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
464 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
485 if (PI.TReg == PI.FReg) {
488 DstReg = PI.TReg;
493 DstReg, Cond, PI.TReg, PI.FReg);
