Lines Matching defs:BrCond
109 /// BrCond - Conditions for end of block conditional branches.
127 SmallVector<MachineOperand, 4> BrCond;
455 if (!TII->ReverseBranchCondition(BBI.BrCond)) {
457 TII->InsertBranch(*BBI.BB, BBI.FalseBB, BBI.TrueBB, BBI.BrCond, dl);
517 if (TrueBBI.TrueBB && TrueBBI.BrCond.empty())
656 BBI.BrCond.clear();
658 !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond);
661 if (BBI.BrCond.size()) {
779 if (BBI.BrCond.size()) {
785 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
832 if (!BBI.IsBrAnalyzable || BBI.BrCond.empty() || BBI.IsDone) {
873 RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
890 FeasibilityAnalysis(TrueBBI, BBI.BrCond) &&
908 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true)) {
924 FeasibilityAnalysis(TrueBBI, BBI.BrCond, true, true)) {
933 FeasibilityAnalysis(TrueBBI, BBI.BrCond)) {
1117 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1204 SmallVector<MachineOperand, 4> Cond(BBI.BrCond.begin(), BBI.BrCond.end());
1282 SmallVector<MachineOperand, 4> RevCond(CvtBBI->BrCond.begin(),
1283 CvtBBI->BrCond.end());
1375 SmallVector<MachineOperand, 4> RevCond(BBI.BrCond.begin(), BBI.BrCond.end());
1378 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond;