Lines Matching refs:Intf
269 InterferenceCache::Cursor Intf;
278 Intf.setPhysReg(Cache, Reg);
753 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
754 assert(TargetRegisterInfo::isVirtualRegister(Intf->reg) &&
757 if (getStage(*Intf) == RS_Done)
766 (Intf->isSpillable() ||
768 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
770 unsigned IntfCascade = ExtraRegInfo[Intf->reg].Cascade;
779 bool BreaksHint = VRM->hasPreferredPhys(Intf->reg);
782 Cost.MaxWeight = std::max(Cost.MaxWeight, Intf->weight);
789 if (!shouldEvict(VirtReg, IsHint, *Intf, BreaksHint))
794 if (!MaxCost.isMax() && IsLocal && LIS->intervalIsInOneMBB(*Intf) &&
795 (!EnableLocalReassign || !canReassign(*Intf, PhysReg))) {
830 LiveInterval *Intf = Intfs[i];
832 if (!VRM->hasPhys(Intf->reg))
834 Matrix->unassign(*Intf);
835 assert((ExtraRegInfo[Intf->reg].Cascade < Cascade ||
836 VirtReg.isSpillable() < Intf->isSpillable()) &&
838 ExtraRegInfo[Intf->reg].Cascade = Cascade;
840 NewVRegs.push_back(Intf->reg);
934 bool RAGreedy::addSplitConstraints(InterferenceCache::Cursor Intf,
946 Intf.moveToBlock(BC.Number);
951 if (!Intf.hasInterference())
959 if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number)) {
962 } else if (Intf.first() < BI.FirstInstr) {
965 } else if (Intf.first() < BI.LastInstr) {
972 if (Intf.last() >= SA->getLastSplitPoint(BC.Number)) {
975 } else if (Intf.last() > BI.LastInstr) {
978 } else if (Intf.last() > BI.FirstInstr) {
998 void RAGreedy::addThroughConstraints(InterferenceCache::Cursor Intf,
1007 Intf.moveToBlock(Number);
1009 if (!Intf.hasInterference()) {
1023 if (Intf.first() <= Indexes->getMBBStartIdx(Number))
1029 if (Intf.last() >= SA->getLastSplitPoint(Number))
1081 addThroughConstraints(Cand.Intf, NewBlocks);
1115 // The static split cost will be zero since Cand.Intf reports no interference.
1117 if (!addSplitConstraints(Cand.Intf, Cost)) {
1188 Cand.Intf.moveToBlock(Number);
1189 if (Cand.Intf.hasInterference()) {
1239 Cand.Intf.moveToBlock(Number);
1240 IntfIn = Cand.Intf.first();
1248 Cand.Intf.moveToBlock(Number);
1249 IntfOut = Cand.Intf.last();
1288 Cand.Intf.moveToBlock(Number);
1289 IntfIn = Cand.Intf.first();
1296 Cand.Intf.moveToBlock(Number);
1297 IntfOut = Cand.Intf.last();
1421 if (!addSplitConstraints(Cand.Intf, Cost)) {
2025 LiveInterval *Intf = Q.interferingVRegs()[i - 1];
2026 // If Intf is done and sit on the same register class as VirtReg,
2028 if ((getStage(*Intf) == RS_Done &&
2029 MRI->getRegClass(Intf->reg) == CurRC) ||
2030 FixedRegisters.count(Intf->reg)) {
2034 RecoloringCandidates.insert(Intf);
