Lines Matching refs:SRA
86 case ISD::SRA: Res = PromoteIntRes_SRA(N); break;
678 return DAG.getNode(ISD::SRA, SDLoc(N), LHS.getValueType(), LHS, RHS);
919 case ISD::SRA:
1394 case ISD::SRA:
1484 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
1486 Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1489 Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
1491 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1495 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH,
1503 Hi = DAG.getNode(ISD::SRA, DL, NVT, InH, DAG.getConstant(Amt, DL, ShTy));
1551 case ISD::SRA:
1552 Hi = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign extend high part.
1554 Lo = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt); // Lo part from Hi part.
1573 case ISD::SRA: Op1 = ISD::SRL; Op2 = ISD::SHL; break;
1657 case ISD::SRA:
1659 HiS = DAG.getNode(ISD::SRA, dl, NVT, InH, Amt);
1665 HiL = DAG.getNode(ISD::SRA, dl, NVT, InH, // Sign of Hi part.
1667 LoL = DAG.getNode(ISD::SRA, dl, NVT, InH, AmtExcess); // Lo from Hi part.
1903 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2074 // The high part is obtained by SRA'ing all but one of the bits of the
2077 Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
2149 Hi = DAG.getNode(ExtType == ISD::SEXTLOAD ? ISD::SRA : ISD::SRL, dl, NVT,
2344 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2400 assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2430 // The high part is obtained by SRA'ing all but one of the bits of low part.
2433 ISD::SRA, dl, NVT, Lo,
2467 Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
2764 case ISD::SRA:
