Lines Matching refs:IdxVal
839 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
841 DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
861 // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
865 unsigned IdxVal = ConstIdx->getZExtValue();
866 if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
986 unsigned IdxVal = CIdx->getZExtValue();
988 if (IdxVal < LoNumElts)
994 DAG.getConstant(IdxVal - LoNumElts, dl,
1602 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1604 if (IdxVal < LoElts) {
1605 assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
1610 DAG.getConstant(IdxVal - LoElts, dl,
1621 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
1622 assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
1629 if (IdxVal < LoElts)
1632 DAG.getConstant(IdxVal - LoElts, SDLoc(N),
2803 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
2804 if (IdxVal == 0 && InVT == WidenVT)
2809 if (IdxVal % WidenNumElts == 0 && IdxVal + WidenNumElts < InNumElts)
2821 DAG.getConstant(IdxVal + i, dl,
