Lines Matching refs:SUB
1136 case ISD::SUB: {
1137 // Add, Sub, and Mul don't demand any bits in positions beyond that
1413 SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp,
1415 SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub);
2008 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2056 if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
2085 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2100 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2111 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2871 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2950 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
3113 SDValue Exponent = DAG.getNode(ISD::SUB, dl, IntVT, ExponentBits, Bias);
3130 DAG.getNode(ISD::SUB, dl, IntVT, Exponent, ExponentLoBit),
3134 DAG.getNode(ISD::SUB, dl, IntVT, ExponentLoBit, Exponent),
3138 SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT,
