Lines Matching defs:Address
45 class Address {
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
142 bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
143 bool computeCallAddress(const Value *V, Address &Addr);
144 bool simplifyAddress(Address &Addr, MVT VT);
145 void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
149 bool tryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
184 unsigned emitLoad(MVT VT, MVT ResultVT, Address Addr, bool WantZExt = true,
186 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
504 // Computes the address to get to an object.
505 bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
525 // address spaces.
549 Address SavedAddr = Addr;
600 Addr.setKind(Address::FrameIndexBase);
619 Address Backup = Addr;
854 bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
948 bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
973 // the alloca address into a register, set the base type back to register and
983 Addr.setKind(Address::RegBase);
1041 void AArch64FastISel::addLoadStoreOperands(Address &Addr,
1058 assert(Addr.isRegBase() && "Unexpected address kind.");
1698 unsigned AArch64FastISel::emitLoad(MVT VT, MVT RetVT, Address Addr,
1914 // See if we can handle this address.
1915 Address Addr;
2000 bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
2112 // See if we can handle this address.
2113 Address Addr;
3004 Address Addr;
3005 Addr.setKind(Address::RegBase);
3116 Address Addr;
3187 bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
3194 Address OrigDest = Dest;
3195 Address OrigSrc = Src;
3344 // Recursively load frame address
3377 Address Dest, Src;
3391 // address spaces.
3408 // address spaces.
