Lines Matching refs:NumVecs
150 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1019 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc,
1029 N->op_begin() + Vec0Off + NumVecs);
1036 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
1134 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
1147 for (unsigned i = 0; i < NumVecs; ++i)
1151 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1155 void AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,
1171 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1175 if (NumVecs == 1)
1178 for (unsigned i = 0; i < NumVecs; ++i)
1183 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1187 void AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
1194 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1197 SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};
1203 void AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,
1212 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1216 N->getOperand(NumVecs + 1), // base register
1217 N->getOperand(NumVecs + 2), // Incremental
1259 void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1266 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1277 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1280 N->getOperand(NumVecs + 3), N->getOperand(0)};
1287 for (unsigned i = 0; i < NumVecs; ++i) {
1294 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1298 void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
1305 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1317 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1322 N->getOperand(NumVecs
1323 N->getOperand(NumVecs + 3), // Incremental
1328 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));
1332 if (NumVecs == 1) {
1339 for (unsigned i = 0; i < NumVecs; ++i) {
1349 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));
1353 void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1360 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1369 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1372 N->getOperand(NumVecs + 3), N->getOperand(0)};
1383 void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
1390 SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);
1402 cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
1405 N->getOperand(NumVecs + 2), // Base Register
1406 N->getOperand(NumVecs + 3), // Incremental
