Lines Matching refs:AArch64TargetLowering
10 // This file implements the AArch64TargetLowering class.
59 AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
634 void AArch64TargetLowering::addTypeForNEON(MVT VT, MVT PromotedBitwiseVT) {
717 void AArch64TargetLowering::addDRTypeForNEON(MVT VT) {
722 void AArch64TargetLowering::addQRTypeForNEON(MVT VT) {
727 EVT AArch64TargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &,
737 void AArch64TargetLowering::computeKnownBitsForTargetNode(
797 MVT AArch64TargetLowering::getScalarShiftAmountTy(const DataLayout &DL,
802 bool AArch64TargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
828 AArch64TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
833 const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
963 AArch64TargetLowering::EmitF128CSEL(MachineInstr &MI,
1022 MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(
1730 SDValue AArch64TargetLowering::LowerF128Call(SDValue Op, SelectionDAG &DAG,
1888 SDValue AArch64TargetLowering::LowerFP_EXTEND(SDValue Op,
1898 SDValue AArch64TargetLowering::LowerFP_ROUND(SDValue Op,
1954 SDValue AArch64TargetLowering::LowerFP_TO_INT(SDValue Op,
2010 SDValue AArch64TargetLowering::LowerINT_TO_FP(SDValue Op,
2042 SDValue AArch64TargetLowering::LowerFSINCOS(SDValue Op,
2280 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2305 SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
2418 CCAssignFn *AArch64TargetLowering::CCAssignFnForCall(CallingConv::ID CC,
2437 SDValue AArch64TargetLowering::LowerFormalArguments(
2636 void AArch64TargetLowering::saveVarArgRegisters(CCState &CCInfo,
2713 SDValue AArch64TargetLowering::LowerCallResult(
2761 bool AArch64TargetLowering::isEligibleForTailCallOptimization(
2868 SDValue AArch64TargetLowering::addTokenForArgument(SDValue Chain,
2901 bool AArch64TargetLowering::DoesCalleeRestoreStack(CallingConv::ID CallCC,
2906 bool AArch64TargetLowering::IsTailCallConvention(CallingConv::ID CallCC) const {
2914 AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
3276 bool AArch64TargetLowering::CanLowerReturn(
3288 AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
3358 SDValue AArch64TargetLowering::LowerGlobalAddress(SDValue Op,
3428 AArch64TargetLowering::LowerDarwinGlobalTLSAddress(SDValue Op,
3487 SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
3503 AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
3603 SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op,
3612 SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3743 SDValue AArch64TargetLowering::LowerFCOPYSIGN(SDValue Op,
3818 SDValue AArch64TargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
3852 SDValue AArch64TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
3924 SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
4065 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
4076 SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
4117 SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
4145 SDValue AArch64TargetLowering::LowerConstantPool(SDValue Op,
4186 SDValue AArch64TargetLowering::LowerBlockAddress(SDValue Op,
4209 SDValue AArch64TargetLowering::LowerDarwin_VASTART(SDValue Op,
4222 SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
4291 SDValue AArch64TargetLowering::LowerVASTART(SDValue Op,
4297 SDValue AArch64TargetLowering::LowerVACOPY(SDValue Op,
4313 SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
4376 SDValue AArch64TargetLowering::LowerFRAMEADDR(SDValue Op,
4394 unsigned AArch64TargetLowering::getRegisterByName(const char* RegName, EVT VT,
4405 SDValue AArch64TargetLowering::LowerRETURNADDR(SDValue Op,
4429 SDValue AArch64TargetLowering::LowerShiftRightParts(SDValue Op,
4487 SDValue AArch64TargetLowering::LowerShiftLeftParts(SDValue Op,
4536 bool AArch64TargetLowering::isOffsetFoldingLegal(
4542 bool AArch64TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4562 const AArch64TargetLowering::DAGCombinerInfo &DCI, unsigned Opcode,
4582 SDValue AArch64TargetLowering::getRecipEstimate(SDValue Operand,
4587 SDValue AArch64TargetLowering::getRsqrtEstimate(SDValue Operand,
4620 const char *AArch64TargetLowering::LowerXConstraint(EVT ConstraintVT) const {
4644 AArch64TargetLowering::ConstraintType
4645 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4668 AArch64TargetLowering::getSingleConstraintMatchWeight(
4695 AArch64TargetLowering::getRegForInlineAsmConstraint(
4754 void AArch64TargetLowering::LowerAsmOperandForConstraint(
4927 SDValue AArch64TargetLowering::ReconstructShuffle(SDValue Op,
5578 SDValue AArch64TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5752 SDValue AArch64TargetLowering::LowerVectorAND(SDValue Op,
5944 SDValue AArch64TargetLowering::LowerVectorOR(SDValue Op,
6069 SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
6445 SDValue AArch64TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op,
6479 AArch64TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
6515 SDValue AArch64TargetLowering
6542 bool AArch64TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
6623 SDValue AArch64TargetLowering::LowerVectorSRA_SRL_SHL(SDValue Op,
6767 SDValue AArch64TargetLowering::LowerVSETCC(SDValue Op,
6821 bool AArch64TargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6935 bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
6942 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
6953 bool AArch64TargetLowering::isProfitableToHoist(Instruction *I) const {
6979 bool AArch64TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const {
6986 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const {
6994 bool AArch64TargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
7009 bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
7063 bool AArch64TargetLowering::hasPairedLoad(Type *LoadedType,
7073 bool AArch64TargetLowering::hasPairedLoad(EVT LoadedType,
7095 bool AArch64TargetLowering::lowerInterleavedLoad(
7178 bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI,
7244 EVT AArch64TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
7274 bool AArch64TargetLowering::isLegalAddImmediate(int64_t Immed) const {
7285 bool AArch64TargetLowering::isLegalICmpImmediate(int64_t Immed) const {
7291 bool AArch64TargetLowering::isLegalAddressingMode(const DataLayout &DL,
7341 int AArch64TargetLowering::getScalingFactorCost(const DataLayout &DL,
7358 bool AArch64TargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7376 AArch64TargetLowering::getScratchRegisters(CallingConv::ID) const {
7387 AArch64TargetLowering::isDesirableToCommuteWithShift(const SDNode *N) const {
7402 bool AArch64TargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
7493 AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9843 SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
9943 bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
9980 bool AArch64TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
9984 bool AArch64TargetLowering::getIndexedAddressParts(SDNode *Op, SDValue &Base,
10006 bool AArch64TargetLowering
10028 bool AArch64TargetLowering::getPostIndexedAddressParts(
10109 void AArch64TargetLowering::ReplaceNodeResults(
10146 bool AArch64TargetLowering::useLoadStackGuardNode() const {
10152 unsigned AArch64TargetLowering::combineRepeatedFPDivisors() const {
10159 AArch64TargetLowering::getPreferredVectorAction(EVT VT) const {
10173 bool AArch64TargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
10182 AArch64TargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
10189 AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
10194 bool AArch64TargetLowering::shouldExpandAtomicCmpXchgInIR(
10204 Value *AArch64TargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
10239 void AArch64TargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
10246 Value *AArch64TargetLowering::emitStoreConditional(IRBuilder<> &Builder,
10278 bool AArch64TargetLowering::functionArgumentNeedsConsecutiveRegisters(
10283 bool AArch64TargetLowering::shouldNormalizeToSelectSequence(LLVMContext &,
10288 Value *AArch64TargetLowering::getIRStackGuard(IRBuilder<> &IRB) const {
10304 Value *AArch64TargetLowering::getSafeStackPointerLocation(IRBuilder<> &IRB) const {
10320 void AArch64TargetLowering::initializeSplitCSR(MachineBasicBlock *Entry) const {
10326 void AArch64TargetLowering::insertCopiesSplitCSR(
10367 bool AArch64TargetLowering::isIntDivCheap(EVT VT, AttributeSet Attr) const {
