Lines Matching refs:Constraint
3031 // satisfy the same constraint.
4621 // At this point, we have to lower this constraint to something else, so we
4623 // to be in register, while the X constraint is much more permissive.
4642 /// getConstraintType - Given a constraint letter, return the type of
4643 /// constraint it is for this target.
4645 AArch64TargetLowering::getConstraintType(StringRef Constraint) const {
4646 if (Constraint.size() == 1) {
4647 switch (Constraint[0]) {
4661 return TargetLowering::getConstraintType(Constraint);
4664 /// Examine constraint type and operand type and determine a weight value.
4666 /// and the current alternative constraint selected.
4669 AsmOperandInfo &info, const char *constraint) const {
4677 // Look at the constraint type.
4678 switch (*constraint) {
4680 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
4696 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
4697 if (Constraint.size() == 1) {
4698 switch (Constraint[0]) {
4711 // The instructions that this constraint is designed for can
4719 if (StringRef("{cc}").equals_lower(Constraint))
4723 // constraint into a member of a register class.
4725 Res = TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4729 unsigned Size = Constraint.size();
4730 if ((Size == 4 || Size == 5) && Constraint[0] == '{' &&
4731 tolower(Constraint[1]) == 'v' && Constraint[Size - 1] == '}') {
4733 bool Failed = Constraint.slice(2, Size - 1).getAsInteger(10, RegNo);
4755 SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
4760 if (Constraint.length() != 1)
4763 char ConstraintLetter = Constraint[0];
4795 // The I constraint applies only to simple ADD or SUB immediate operands:
4797 // The J constraint applies only to ADD or SUB immediates that would be
4886 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
