Lines Matching refs:SUB
199 // Add/Sub overflow ops with MVT::Glues are lowered to NZCV dependences.
238 // Custom lower Add/Sub/Mul with overflow.
464 // Vector add and sub nodes may conceal a high-half opportunity.
467 setTargetDAGCombine(ISD::SUB);
1225 if (RHS.getOpcode() == ISD::SUB && isNullConstant(RHS.getOperand(0)) &&
1227 // We'd like to combine a (CMP op1, (sub 0, op2) into a CMN instruction on
1308 } else if (RHS.getOpcode() == ISD::SUB) {
2191 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
2202 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
3634 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a branch
3975 } else if (TVal.getOpcode() == ISD::SUB) {
3976 // If TVal is a negation (SUB from 0) we want to swap TVal and FVal so
4084 // Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
4442 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4455 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4498 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64,
4511 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i64, ShAmt,
4605 // J - Constant that can be used with a SUB instruction
4795 // The I constraint applies only to simple ADD or SUB immediate operands:
4797 // The J constraint applies only to ADD or SUB immediates that would be
4798 // valid when negated, i.e. if [an add pattern] were to be output as a SUB
7019 // addressing mode or an arithmetic operation: add, sub, and cmp.
7171 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
7172 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
7173 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
7174 /// call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)
7228 // Split the shufflevector operands into sub vectors for the new stN call.
7278 // Same encoding for add/sub, just flip the sign.
7284 // immediates is the same as for an add or a sub.
7461 // and change it to SUB and CSEL.
7467 SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
7535 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), SRA);
7545 // cheaply as as shift+add/sub. For now, this is true unilaterally. If
7563 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7569 return DAG.getNode(ISD::SUB, DL, VT, ShiftedVal,
7573 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7579 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0),
7590 return DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Add);
8356 // The basic add/sub long vector instructions have variants with "2" on the end
9418 // sub w8, w0, w1
9850 case ISD::SUB:
9989 if (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)
