Lines Matching defs:AMDGPUTargetLowering
49 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
58 EVT AMDGPUTargetLowering::getEquivalentBitType(LLVMContext &Ctx, EVT VT) {
66 AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
491 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {
495 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {
501 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
507 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {
512 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,
535 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,
554 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {
558 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {
566 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {
571 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {
576 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,
582 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {
594 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {
599 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
605 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {
612 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {
620 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
624 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
638 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,
644 void AMDGPUTargetLowering::AnalyzeReturn(CCState &State,
651 AMDGPUTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
663 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,
687 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
698 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,
731 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,
758 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,
844 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
895 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
905 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
917 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
951 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(const SDLoc &DL, EVT VT,
1028 AMDGPUTargetLowering::split64BitValue(SDValue Op, SelectionDAG &DAG) const {
1042 SDValue AMDGPUTargetLowering::getLoHalf64(SDValue Op, SelectionDAG &DAG) const {
1050 SDValue AMDGPUTargetLowering::getHiHalf64(SDValue Op, SelectionDAG &DAG) const {
1058 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,
1116 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,
1174 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,
1231 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG,
1334 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
1412 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,
1527 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
1588 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {
1603 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {
1643 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {
1692 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {
1719 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {
1727 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {
1755 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {
1812 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {
1824 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {
1849 SDValue AMDGPUTargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const {
1903 SDValue AMDGPUTargetLowering::LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG,
1988 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,
2011 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,
2026 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,
2041 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,
2070 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,
2080 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,
2090 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
2172 bool AMDGPUTargetLowering
2193 SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
2241 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
2291 SDValue AMDGPUTargetLowering::performAndCombine(SDNode *N,
2332 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,
2366 SDValue AMDGPUTargetLowering::performSraCombine(SDNode *N,
2401 SDValue AMDGPUTargetLowering::performSrlCombine(SDNode *N,
2436 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,
2505 SDValue AMDGPUTargetLowering::performCtlzCombine(const SDLoc &SL, SDValue Cond,
2535 SDValue AMDGPUTargetLowering::performSelectCombine(SDNode *N,
2561 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,
2733 void AMDGPUTargetLowering::getOriginalFunctionArgs(
2765 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
2780 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(
2794 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
2877 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,
2895 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,
2917 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
2956 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
