Lines Matching refs:SITargetLowering
55 SITargetLowering::SITargetLowering(const TargetMachine &TM,
258 const SISubtarget *SITargetLowering::getSubtarget() const {
266 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
285 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
292 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
298 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
333 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
429 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
477 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
503 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
508 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
525 SITargetLowering::getPreferredVectorAction(EVT VT) const {
532 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
538 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
548 SDValue SITargetLowering::LowerParameterPtr(SelectionDAG &DAG,
563 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
588 SDValue SITargetLowering::LowerFormalArguments(
938 SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1029 unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
1077 MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
1131 MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
1164 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1175 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
1183 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
1202 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
1228 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1278 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
1315 bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
1332 void SITargetLowering::createDebuggerPrologueStackObjects(
1360 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1441 SDValue SITargetLowering::getSegmentAperture(unsigned AS,
1472 SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
1529 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1560 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1590 SDValue SITargetLowering::lowerTRAP(SDValue Op,
1607 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
1623 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1651 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1919 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
1942 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1996 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2087 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2116 SDValue SITargetLowering::LowerFastFDIV(SDValue Op, SelectionDAG &DAG) const {
2157 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
2225 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
2292 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
2304 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2362 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
2382 SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
2413 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
2484 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
2517 SDValue SITargetLowering::performAndCombine(SDNode *N,
2574 SDValue SITargetLowering::performOrCombine(SDNode *N,
2634 SDValue SITargetLowering::performClassCombine(SDNode *N,
2652 SDValue SITargetLowering::performFCanonicalizeCombine(
2766 SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
2827 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
2858 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
3068 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
3104 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
3195 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
3215 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
3234 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3310 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
3345 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
3375 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
3389 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3448 SITargetLowering::ConstraintType
3449 SITargetLowering::getConstraintType(StringRef Constraint) const {
