Lines Matching refs:Op
103 bool isOpRelevant(MachineOperand &Op);
225 bool SIInsertWaits::isOpRelevant(MachineOperand &Op) {
227 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()))
231 if (Op.isDef())
235 MachineInstr &MI = *Op.getParent();
250 if (Data && Op.isIdenticalTo(*Data))
256 if (Data0 && Op.isIdenticalTo(*Data0))
260 return Data1 && Op.isIdenticalTo(*Data1);
269 return Op.isIdenticalTo(*I);
337 MachineOperand &Op = I->getOperand(i);
338 if (!isOpRelevant(Op))
342 RegInterval Interval = getRegInterval(RC, Op);
346 if (Op.isDef())
350 if (Op.isUse())
467 MachineOperand &Op = MI.getOperand(i);
468 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()))
472 RegInterval Interval = getRegInterval(RC, Op);
475 if (Op.isDef()) {
480 if (Op.isUse())
505 const MachineOperand &Op = I->getOperand(i);
507 if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0)
