Lines Matching defs:ARMBaseInstrInfo
1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
15 #include "ARMBaseInstrInfo.h"
86 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
100 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
110 ScheduleHazardRecognizer *ARMBaseInstrInfo::
118 MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(
293 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
385 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
409 unsigned ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB,
450 bool ARMBaseInstrInfo::
457 ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
473 bool ARMBaseInstrInfo::PredicateInstruction(
494 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
520 bool ARMBaseInstrInfo::DefinesPredicate(
574 bool ARMBaseInstrInfo::isPredicable(MachineInstr &MI) const {
613 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const {
666 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
677 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
698 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
720 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
852 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
863 void ARMBaseInstrInfo::
997 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1040 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1046 void ARMBaseInstrInfo::
1179 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1222 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1230 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1233 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1281 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1406 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
1434 MachineInstr *ARMBaseInstrInfo::duplicate(MachineInstr &Orig,
1450 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
1545 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1626 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1656 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1699 bool ARMBaseInstrInfo::
1742 bool ARMBaseInstrInfo::
1766 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1800 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,
1864 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,
1886 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
2002 const ARMBaseInstrInfo &TII,
2145 const ARMBaseInstrInfo &TII) {
2287 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
2391 bool ARMBaseInstrInfo::optimizeCompareInstr(
2639 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
3021 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {
3070 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3184 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3225 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3260 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3300 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3329 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3673 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3709 int ARMBaseInstrInfo::getOperandLatencyImpl(
3770 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3985 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4003 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4053 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4071 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4092 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4108 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4119 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4149 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4184 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
4274 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
4482 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
4543 void ARMBaseInstrInfo::breakPartialRegDependency(
4577 bool ARMBaseInstrInfo::hasNOP() const {
4581 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4595 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4620 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4641 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
