Cross Reference: /external/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

Lines Matching defs:AddDReg
852 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
899           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
900           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
910           AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
911           AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
946           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
947           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
948           AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
967           MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
968           MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
969           MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
970                 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
981         MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
982         MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
983         MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
984         MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
985         MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
986         MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
987         MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
988               AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1081         AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1082         AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1091         MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1092         MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1125         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1126         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1127         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1145         MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1146         MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1147         MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1148         MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1161       MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1162       MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1163       MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1164       MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1165       MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1166       MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1167       MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1168       MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
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