Lines Matching refs:NextReg
1128 unsigned NextReg = ARM::D8;
1133 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1139 .addReg(NextReg)
1141 NextReg += 4;
1147 unsigned R4BaseReg = NextReg;
1151 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1155 .addReg(ARM::R4).addImm(16).addReg(NextReg)
1157 NextReg += 4;
1163 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1168 NextReg += 2;
1174 MBB.addLiveIn(NextReg);
1177 .addReg(NextReg)
1178 .addReg(ARM::R4).addImm((NextReg-R4BaseReg)*2));
1247 unsigned NextReg = ARM::D8;
1251 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1253 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1257 NextReg += 4;
1263 unsigned R4BaseReg = NextReg;
1267 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1269 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1272 NextReg += 4;
1278 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0,
1282 NextReg += 2;
1288 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
1289 .addReg(ARM::R4).addImm(2*(NextReg-R4BaseReg)));
