Lines Matching refs:NumVecs
200 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
203 /// For NumVecs <= 2, QOpcodes1 is not used.
204 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
208 /// SelectVST - Select NEON store intrinsics. NumVecs should
211 /// For NumVecs <= 2, QOpcodes1 is not used.
212 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
216 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
220 unsigned NumVecs, const uint16_t *DOpcodes,
223 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
226 void SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
229 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
232 void SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
268 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1688 unsigned NumVecs, bool is64BitVector) {
1689 unsigned NumRegs = NumVecs;
1690 if (!is64BitVector && NumVecs < 3)
1808 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1812 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1823 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1841 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1846 if (NumVecs == 1)
1849 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1866 if (is64BitVector || NumVecs <= 2) {
1875 if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode()))
1879 if ((NumVecs > 2 && !isVLDfixed(Opc)) ||
1924 if (NumVecs == 1) {
1935 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1938 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1940 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1944 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1948 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1963 Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);
1981 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1995 if (is64BitVector || NumVecs <= 2) {
1997 if (NumVecs == 1) {
2003 if (NumVecs == 2)
2009 SDValue V3 = (NumVecs == 3)
2029 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
2035 else if (NumVecs > 2 && !isVSTfixed(Opc))
2058 SDValue V3 = (NumVecs == 3)
2093 unsigned NumVecs,
2096 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2110 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2115 if (NumVecs != 3) {
2117 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2145 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2169 if (NumVecs == 2) {
2176 SDValue V3 = (NumVecs == 3)
2205 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2208 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2210 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2214 void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
2216 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2230 if (NumVecs != 3) {
2232 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2267 else if (NumVecs > 2)
2274 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2287 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2290 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2292 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2296 void ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2298 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2307 if (NumVecs == 2)
2313 SDValue V3 = (NumVecs == 3)
2323 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
