Lines Matching refs:DispatchBB
7284 MachineBasicBlock *DispatchBB,
7300 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
7463 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
7464 DispatchBB->setIsEHPad();
7474 DispatchBB->addSuccessor(TrapBB);
7477 DispatchBB->addSuccessor(DispContBB);
7480 MF->insert(MF->end(), DispatchBB);
7486 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
7493 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
7506 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
7512 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
7517 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
7523 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
7528 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
7533 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
7556 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
7562 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
7577 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
7580 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
7585 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
7629 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
7635 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
7640 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
7646 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
7651 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7666 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
7670 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7675 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
7737 BB->addSuccessor(DispatchBB, BranchProbability::getZero());