Lines Matching refs:NewVReg1
7322 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7323 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
7330 .addReg(NewVReg1, RegState::Kill)
7349 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7350 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
7355 .addReg(NewVReg1, RegState::Kill)
7381 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7382 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
7388 .addReg(NewVReg1, RegState::Kill)
7505 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7506 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
7513 .addReg(NewVReg1)
7529 .addReg(NewVReg1)
7547 .addReg(NewVReg1)
7552 .addReg(NewVReg1)
7555 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7556 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
7563 .addReg(NewVReg1)
7581 .addReg(NewVReg1)
7593 .addReg(NewVReg1)
7628 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7629 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
7636 .addReg(NewVReg1)
7652 .addReg(NewVReg1)
7671 .addReg(NewVReg1)
7683 .addReg(NewVReg1)
