Lines Matching refs:PredReg
150 ARMCC::CondCodes Pred, unsigned PredReg);
154 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
159 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
460 unsigned PredReg) {
528 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
546 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg);
596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
711 .addImm(Pred).addReg(PredReg);
721 .addImm(Pred).addReg(PredReg);
726 .addImm(Pred).addReg(PredReg);
730 .addImm(Pred).addReg(PredReg).addReg(0);
774 UpdateBaseRegUses(MBB, InsertBefore, DL, Base, NumRegs, Pred, PredReg);
782 MIB.addImm(Pred).addReg(PredReg);
793 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL,
809 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
860 unsigned PredReg = 0;
861 ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg);
866 Opcode, Pred, PredReg, DL, Regs);
869 Opcode, Pred, PredReg, DL, Regs);
1127 ARMCC::CondCodes Pred, unsigned PredReg) {
1146 MIPredReg != PredReg)
1157 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {
1170 Offset = isIncrementOrDecrement(*PrevMBBI, Reg, Pred, PredReg);
1177 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) {
1188 Offset = isIncrementOrDecrement(*NextMBBI, Reg, Pred, PredReg);
1211 unsigned PredReg = 0;
1212 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1227 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1234 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);
1265 .addImm(Pred).addReg(PredReg);
1353 unsigned PredReg = 0;
1354 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1360 = findIncDecBefore(MBBI, Base, Pred, PredReg, Offset);
1367 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);
1389 .addImm(Pred).addReg(PredReg)
1398 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1403 .addReg(Base).addReg(0).addImm(Imm).addImm(Pred).addReg(PredReg);
1409 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1421 .addReg(Base).addReg(0).addImm(Imm).addImm(Pred).addReg(PredReg);
1426 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1450 unsigned PredReg;
1451 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
1456 PredReg, Offset);
1461 MergeInstr = findIncDecAfter(MBBI, Base, Pred, PredReg, Offset);
1480 .addImm(Offset).addImm(Pred).addReg(PredReg);
1555 unsigned PredReg, const TargetInstrInfo *TII,
1562 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1568 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1610 unsigned PredReg = 0;
1611 ARMCC::CondCodes Pred = getInstrPredicate(*MI, PredReg);
1622 .addImm(Pred).addReg(PredReg)
1629 .addImm(Pred).addReg(PredReg)
1656 Pred, PredReg, TII, isT2);
1660 Pred, PredReg, TII, isT2);
1675 Pred, PredReg, TII, isT2);
1679 Pred, PredReg, TII, isT2);
1716 unsigned PredReg = 0;
1717 ARMCC::CondCodes Pred = getInstrPredicate(*MBBI, PredReg);
1727 // Note: No need to match PredReg in the next if.
1976 unsigned &PredReg, ARMCC::CondCodes &Pred,
2060 unsigned &PredReg,
2124 Pred = getInstrPredicate(*Op0, PredReg);
2218 unsigned BaseReg = 0, PredReg = 0;
2226 Offset, PredReg, Pred, isT2)) {
2246 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2260 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2317 unsigned PredReg = 0;
2318 if (getInstrPredicate(MI, PredReg) != ARMCC::AL)
