Lines Matching refs:Entry
159 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
164 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
169 const ReduceEntry &Entry);
172 const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
177 const ReduceEntry &Entry, bool LiveCPSR,
183 const ReduceEntry &Entry, bool LiveCPSR,
306 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
309 if ((is2Addr && Entry.PredCC2 == 0) ||
310 (!is2Addr && Entry.PredCC1 == 0)) {
329 } else if ((is2Addr && Entry.PredCC2 == 2) ||
330 (!is2Addr && Entry.PredCC1 == 2)) {
379 const ReduceEntry &Entry) {
388 unsigned Opc = Entry.NarrowOpc1;
390 uint8_t ImmLimit = Entry.Imm1Limit;
392 switch (Entry.WideOpc) {
398 Opc = Entry.NarrowOpc2;
399 ImmLimit = Entry.Imm2Limit;
436 bool IsStore = Entry.WideOpc == ARM::t2STR_POST;
450 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
501 Opc = Entry.NarrowOpc2; // tPOP_RET
513 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
514 Entry.WideOpc == ARM::t2STMDB_UPD)) {
515 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
518 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
519 Entry.WideOpc != ARM::t2STMIA_UPD)) {
557 if (Entry.WideOpc == ARM::t2STMIA)
593 const ReduceEntry &Entry,
600 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
602 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
637 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
641 return ReduceLoadStore(MBB, MI, Entry);
652 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
657 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
669 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
675 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
681 // are prioritized, but the table assumes a unique entry for each
682 // source insn opcode. So for now, we hack a local entry record to use.
687 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
695 const ReduceEntry &Entry,
701 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
737 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
739 if (Entry.Imm2Limit) {
741 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
746 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
751 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
772 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
777 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
814 const ReduceEntry &Entry,
819 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
825 if (Entry.Imm1Limit)
826 Limit = (1 << Entry.Imm1Limit) - 1;
837 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
847 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
867 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
872 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
961 const ReduceEntry &Entry = ReduceTable[OPI->second];
964 if (Entry.Special)
965 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
968 if (Entry.NarrowOpc2 &&
969 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
973 if (Entry.NarrowOpc1 &&
974 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
