Lines Matching refs:Op
216 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
217 Sub(Op.getSubReg()) {}
350 for (auto &Op : MI->operands()) {
351 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg)
353 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
357 Op.setIsKill(true);
411 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> bool {
412 if (!Op.isReg() || !Op.isDef())
414 unsigned DR = Op.getReg(), DSR = Op.getSubReg();
494 for (auto &Op : DefI->operands()) {
495 if (Seg.start.isDead() || !IsRegDef(Op))
497 DefRegs.insert(Op);
498 Op.setIsDead(false);
518 for (auto &Op : DefI->operands())
519 if (Op.isReg() && Op.isDef() && DefRegs.count(Op))
520 ImpUses.insert(Op);
694 for (auto &Op : MI.operands())
695 if (Op.isReg())
696 UpdRegs.insert(Op.getReg());
725 for (auto &Op : MI->operands()) {
726 if (!Op.isReg() || !Op.isDef())
762 for (auto &Op : MI->operands()) {
763 if (!Op.isReg() || !Op.isDef())
765 RegisterRef RR = Op;
797 for (auto &Op : MI.operands()) {
798 if (!Op.isReg())
800 RegisterRef RR = Op;
810 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
907 for (auto &Op : NewI->operands())
908 if (Op.isReg())
909 UpdRegs.insert(Op.getReg());
929 for (auto &Op : MI->operands()) {
930 if (!Op.isReg() || RO != RegisterRef(Op))
932 Op.setReg(RN.Reg);
933 Op.setSubReg(RN.Sub);
935 assert(!Op.isDef() && "Not expecting a def");
1001 for (auto &Op : MI->operands()) {
1002 if (!Op.isReg())
1011 RegisterRef RR = Op;
1015 ReferenceMap &Map = Op.isDef() ? Defs : Uses;
1085 for (auto &Op : I->operands())
1086 if (Op.isReg())
1087 UpdRegs.insert(Op.getReg());
