Lines Matching refs:Op
187 for (auto &Op : MI->operands()) {
188 if (!Op.isReg())
190 unsigned R = Op.getReg();
230 MachineOperand &Op = *U;
231 MachineInstr *UseI = Op.getParent();
237 if (&MO == &Op || !MO.isReg() || MO.getSubReg())
305 for (const auto &Op : MI->operands())
306 if (!Op.getSubReg())
396 for (auto &Op : UseI->operands()) {
397 if (Op.isReg() && Part.count(Op.getReg()))
398 if (Op.getSubReg())
554 for (auto &Op : MI->operands()) {
555 if (!Op.isReg()) {
556 NewI->addOperand(Op);
560 unsigned R = Op.getReg();
561 unsigned SR = Op.getSubReg();
563 bool isKill = Op.isKill();
575 auto CO = MachineOperand::CreateReg(R, Op.isDef(), Op.isImplicit(), isKill,
576 Op.isDead(), Op.isUndef(), Op.isEarlyClobber(), SR, Op.isDebug(),
577 Op.isInternalRead());
1040 for (auto &Op : MI->operands()) {
1041 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())
1043 unsigned R = Op.getReg();
1048 switch (Op.getSubReg()) {
1050 Op.setReg(P.first);
1053 Op.setReg(P.second);
1056 Op.setSubReg(0);
1066 for (auto &Op : MI->operands()) {
1067 if (!Op.isReg() || !Op.isUse())
1069 unsigned R = Op.getReg();
1072 if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
1084 Op.setReg(NewDR);
