Lines Matching defs:HII
88 const HexagonInstrInfo *HII;
109 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
177 HII = MF.getSubtarget<HexagonSubtarget>().getInstrInfo();
184 HII->genAllInsnTimingClasses(MF);
222 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
227 while (RE != End && !HII->isSchedulingBoundary(*RE, &MB, MF))
259 auto *ExtMI = MF.CreateMachineInstr(HII->get(Hexagon::A4_ext), DebugLoc());
274 if (HII->isDeallocRet(MI))
284 if (HII->isIndirectCall(MI) && (DepType == SDep::Data)) {
329 return HII->isCondInst(MI) || MI->isReturn() || HII->mayBeNewStore(MI);
339 int CurOpcode = HII->getDotCurOp(MI);
340 MI->setDesc(HII->get(CurOpcode));
361 MI->setDesc(HII->get(Hexagon::V6_vL32b_ai));
369 if (!HII->isV60VectorInstruction(MI))
371 if (!HII->isV60VectorInstruction(&*MII))
375 if (HII->isDotCurInst(MI) && !HII->mayBeCurLoad(MI))
378 if (!HII->mayBeCurLoad(MI))
424 NewOpcode = HII->getDotNewPredOp(MI, MBPI);
426 NewOpcode = HII->getDotNewOp(MI);
427 MI->setDesc(HII->get(NewOpcode));
432 int NewOpcode = HII->getDotOldOp(MI->getOpcode());
433 MI->setDesc(HII->get(NewOpcode));
446 const HexagonInstrInfo *HII) {
447 if (!HII->isPredicated(MI))
449 if (HII->isPredicatedTrue(MI))
455 const HexagonInstrInfo *HII) {
456 assert(HII->isPostIncrement(MI) && "Not a post increment operation.");
533 if (!HII->mayBeNewStore(MI))
544 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
559 if (HII->isPostIncrement(MI) &&
560 getPostIncrementOperand(MI, HII).getReg() == DepReg) {
564 if (HII->isPostIncrement(PacketMI) && PacketMI->mayLoad() &&
565 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
579 if (HII->isPredicated(*PacketMI)) {
580 if (!HII->isPredicated(*MI))
622 HII->isDotNewInst(PacketMI) != HII->isDotNewInst(MI) ||
623 getPredicateSense(*MI, HII) != getPredicateSense(*PacketMI, HII))
662 if (!HII->isPostIncrement(MI)) {
700 if (!HII->mayBeNewStore(MI))
729 if (HII->isDotNewInst(MI) && !HII->mayBeNewStore(MI))
752 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
760 if (HII->isCondInst(MI) || MI->isReturn())
761 return HII->predCanBeUsedAsDotNew(PI, DepReg);
763 if (RC != &Hexagon::PredRegsRegClass && !HII->mayBeNewStore(MI))
768 int NewOpcode = HII->getDotNewOp(MI);
769 const MCInstrDesc &D = HII->get(NewOpcode);
802 if (!HII->isPredicated(*I))
848 if (getPredicateSense(MI1, HII) == PK_Unknown ||
849 getPredicateSense(MI2, HII) == PK_Unknown)
901 unsigned PReg1 = getPredicatedRegister(MI1, HII);
902 unsigned PReg2 = getPredicatedRegister(MI2, HII);
906 getPredicateSense(MI1, HII) != getPredicateSense(MI2, HII) &&
907 HII->isDotNewInst(&MI1) == HII->isDotNewInst(&MI2);
961 if (HII->isSolo(&MI))
979 const HexagonInstrInfo &HII) {
982 HII.isHVXMemWithAIndirect(MI, MJ))
1002 return cannotCoexistAsymm(MI, MJ, *HII) || cannotCoexistAsymm(MJ, MI, *HII);
1054 if (HII->isPredicated(*I) || HII->isPredicated(*J))
1078 if ((HII->isSaveCalleeSavedRegsCall(I) &&
1080 (HII->isSaveCalleeSavedRegsCall(J) &&
1092 if (MI->isCall() || HII->isDeallocRet(MI) || HII->isNewValueJump(MI))
1094 if (HII->isPredicated(*MI) && HII->isPredicatedNew(*MI) && HII->isJumpR(MI))
1099 if (HII->isLoopN(I) && isBadForLoopN(J))
1101 if (HII->isLoopN(J) && isBadForLoopN(I))
1106 return HII->isDeallocRet(I) &&
1118 if (HII->isNewValueInst(J) || HII->isMemOp(J) || HII->isMemOp(I))
1123 bool MopStI = HII->isMemOp(I) || StoreI;
1124 bool MopStJ = HII->isMemOp(J) || StoreJ;
1129 return (StoreJ && HII->isDeallocRet(I)) || (StoreI && HII->isDeallocRet(J));
1167 if (NextMII != I->getParent()->end() && HII->isNewValueJump(&*NextMII)) {
1194 HII->isLoopN(PI)) {
1251 if (I->isCall() || I->isReturn() || HII->isTailCall(I)) {
1265 if (DepType == SDep::Data && HII->isDotCurInst(J)) {
1266 if (HII->isV60VectorInstruction(I))
1278 if (HII->isNewValueJump(I))
1284 if (HII->isPredicated(*I) && HII->isPredicated(*J) &&
1394 if (HII->isValidOffset(Opc, NewOff)) {
1489 bool ExtMI = HII->isExtended(&MI) || HII->isConstExtended(&MI);
1502 bool ExtNvjMI = HII->isExtended(&NvjMI) || HII->isConstExtended(&NvjMI);
1588 if (HII->isV60VectorInstruction(I)) {
1590 if (!HII->isV60VectorInstruction(J))
1592 if (isDependent(J, I) && !HII->isVecUsableNextPacket(J, I))
1602 if (!HII->isV60VectorInstruction(J) && isDependent(J, I))
1608 if (HII->isV60VectorInstruction(J))
1610 if (!HII->isLateInstrFeedsEarlyInstr(J, I))
1612 if (isDependent(J, I) && !HII->canExecuteInBundle(J, I))
