Lines Matching refs:TOut
1511 MipsTargetStreamer &TOut = getTargetStreamer();
1674 TOut.emitRRX(Mips::LW, Mips::T9, Mips::GP,
1676 TOut.emitRRX(Mips::ADDiu, Mips::T9, Mips::T9,
1687 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9,
1699 TOut.emitRRX(ABI.ArePtrs64bit() ? Mips::LD : Mips::LW, Mips::T9, Mips::GP,
1771 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
1884 TOut.emitDirectiveSetNoReorder();
1901 TOut.setUsesMicroMips();
1906 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst.getOpcode()), IDLoc, STI);
1907 TOut.emitDirectiveSetReorder();
1918 TOut.emitEmptyDelaySlot(hasShortDelaySlot(Inst.getOpcode()), IDLoc,
1922 TOut.emitGPRestore(CpRestoreOffset, IDLoc, STI);
2086 MipsTargetStreamer &TOut = getTargetStreamer();
2123 TOut.emitEmptyDelaySlot(hasShortDelaySlot(JalrInst.getOpcode()), IDLoc,
2150 MipsTargetStreamer &TOut = getTargetStreamer();
2195 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2199 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2213 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI);
2227 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2228 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
2230 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2236 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2237 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
2239 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2241 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2245 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
2247 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2249 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2265 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
2266 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
2269 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2292 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2293 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
2303 TOut.emitDSLL(TmpReg, TmpReg, ShiftCarriedForwards, IDLoc, STI);
2306 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI);
2364 MipsTargetStreamer &TOut = getTargetStreamer();
2387 TOut.emitRRX(Mips::LW, DstReg, ABI.GetGlobalPtr(),
2427 TOut.emitRRX(Mips::LW, TmpReg, ABI.GetGlobalPtr(),
2431 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
2435 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
2469 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
2471 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
2473 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
2474 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
2476 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
2477 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
2479 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
2492 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
2494 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
2495 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
2497 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
2499 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
2500 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
2502 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
2527 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
2528 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
2532 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
2543 MipsTargetStreamer &TOut = getTargetStreamer();
2580 TOut.emitEmptyDelaySlot(true, IDLoc, STI);
2587 MipsTargetStreamer &TOut = getTargetStreamer();
2613 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
2626 TOut.emitRRX(OpCode, DstRegOp.getReg(), ATReg, MemOffsetOp, IDLoc, STI);
2643 MipsTargetStreamer &TOut = getTargetStreamer();
2658 TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
2670 TOut.emitLoadWithImmOffset(Inst.getOpcode(), DstReg, BaseReg,
2683 TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
2694 TOut.emitLoadWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
2701 MipsTargetStreamer &TOut = getTargetStreamer();
2707 TOut.emitStoreWithImmOffset(Inst.getOpcode(), SrcReg, BaseReg,
2722 TOut.emitStoreWithSymOffset(Inst.getOpcode(), SrcReg, BaseReg, HiOperand,
2758 MipsTargetStreamer &TOut = getTargetStreamer();
2893 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2898 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2904 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2910 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
2915 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
2922 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2947 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
2965 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
2973 TOut.emitRX(IsSrcRegZero ? ZeroSrcOpcode : ZeroTrgOpcode,
3003 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
3007 TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
3017 MipsTargetStreamer &TOut = getTargetStreamer();
3051 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
3055 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
3059 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
3068 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
3072 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
3084 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
3089 TOut.emitRRI(Mips::BNE, RtReg, ZeroReg, BranchTargetNoTraps, IDLoc, STI);
3092 TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
3095 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
3098 TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
3106 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
3109 TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
3110 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
3111 TOut.emitRRI(Mips::DSLL32, ATReg, ATReg, 0x1f, IDLoc, STI);
3114 TOut.emitRRI(Mips::BNE, RtReg, ATReg, BranchTarget, IDLoc, STI);
3115 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
3119 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
3122 TOut.emitRRI(Mips::BNE, RsReg, ATReg, BranchTargetNoTraps, IDLoc, STI);
3123 TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI);
3124 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
3126 TOut.emitR(Mips::MFLO, RdReg, IDLoc, STI);
3133 MipsTargetStreamer &TOut = getTargetStreamer();
3147 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
3148 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
3149 TOut.emitNop(IDLoc, STI);
3150 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
3151 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
3152 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
3153 TOut.emitNop(IDLoc, STI);
3154 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
3157 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
3158 TOut.emitNop(IDLoc, STI);
3162 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
3171 MipsTargetStreamer &TOut = getTargetStreamer();
3217 TOut.emitAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), STI);
3235 TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
3238 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc,
3241 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
3243 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
3250 MipsTargetStreamer &TOut = getTargetStreamer();
3293 TOut.emitAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), STI);
3306 TOut.emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc,
3309 TOut.emitRRI(Mips::LWR, DstRegOp.getReg(), FinalSrcReg, RightLoadOffset,
3318 MipsTargetStreamer &TOut = getTargetStreamer();
3374 TOut.emitRRR(FinalOpcode, DstReg, DstReg, SrcReg, IDLoc, STI);
3376 TOut.emitRRR(FinalOpcode, FinalDstReg, FinalDstReg, DstReg, IDLoc, STI);
3384 MipsTargetStreamer &TOut = getTargetStreamer();
3403 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3404 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
3409 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
3435 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3436 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
3437 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
3438 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
3449 MipsTargetStreamer &TOut = getTargetStreamer();
3465 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
3470 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
3480 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI);
3501 TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue, Inst.getLoc(), STI);
3502 TOut.emitRRI(SecondShift, DReg, SReg, 32 - ImmValue, Inst.getLoc(), STI);
3503 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
3513 MipsTargetStreamer &TOut = getTargetStreamer();
3532 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3533 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
3538 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
3564 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
3565 TOut.emitRRR(FirstShift, ATReg, SReg, ATReg, Inst.getLoc(), STI);
3566 TOut.emitRRR(SecondShift, DReg, SReg, TReg, Inst.getLoc(), STI);
3567 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
3578 MipsTargetStreamer &TOut = getTargetStreamer();
3612 TOut.emitRRI(FinalOpcode, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
3620 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI);
3661 TOut.emitRRI(FirstShift, ATReg, SReg, ImmValue % 32, Inst.getLoc(), STI);
3662 TOut.emitRRI(SecondShift, DReg, SReg, (32 - ImmValue % 32) % 32,
3664 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
3674 MipsTargetStreamer &TOut = getTargetStreamer();
3678 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
3680 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
3682 TOut.emitEmptyDelaySlot(false, IDLoc, STI);
3683 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
