Lines Matching refs:Constraint
555 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
556 if (Constraint.size() == 1) {
557 switch (Constraint[0]) {
583 return TargetLowering::getConstraintType(Constraint);
588 const char *constraint) const {
596 // Look at the constraint type.
597 switch (*constraint) {
599 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
648 // Parse a "{tNNN}" register constraint for which the register type "t"
652 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
654 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
655 if (isdigit(Constraint[2])) {
658 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
667 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
668 if (Constraint.size() == 1) {
669 // GCC Constraint Letters
670 switch (Constraint[0]) {
698 if (Constraint.size() > 0 && Constraint[0] == '{') {
703 if (Constraint[1] == 'r') {
705 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
708 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
710 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
713 if (Constraint[1] == 'f') {
715 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
718 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
720 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
724 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
728 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
732 if (Constraint.length() == 1) {
733 switch (Constraint[0]) {
770 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
