Lines Matching refs:OPCODE
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
50 // The opcode that should be used to compare Op0 and Op1.
51 unsigned Opcode;
56 // The mask of CC values that Opcode can produce.
271 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
272 if (getOperationAction(Opcode, VT) == Legal)
273 setOperationAction(Opcode, VT, Expand);
1289 // as its only (other) argument. Provide the associated SystemZISD opcode and
1291 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1296 Opcode = SystemZISD::TBEGIN;
1301 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1306 Opcode = SystemZISD::TEND;
1317 // opcode and the mask of valid CC values if so.
1318 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1324 Opcode = SystemZISD::PACKS_CC;
1331 Opcode = SystemZISD::PACKLS_CC;
1339 Opcode = SystemZISD::VICMPES;
1347 Opcode = SystemZISD::VICMPHS;
1355 Opcode = SystemZISD::VICMPHLS;
1360 Opcode = SystemZISD::VTM;
1367 Opcode = SystemZISD::VFAE_CC;
1374 Opcode = SystemZISD::VFAEZ_CC;
1381 Opcode = SystemZISD::VFEE_CC;
1388 Opcode = SystemZISD::VFEEZ_CC;
1395 Opcode = SystemZISD::VFENE_CC;
1402 Opcode = SystemZISD::VFENEZ_CC;
1409 Opcode = SystemZISD::VISTR_CC;
1416 Opcode = SystemZISD::VSTRC_CC;
1423 Opcode = SystemZISD::VSTRCZ_CC;
1428 Opcode = SystemZISD::VFCMPES;
1433 Opcode = SystemZISD::VFCMPHS;
1438 Opcode = SystemZISD::VFCMPHES;
1443 Opcode = SystemZISD::VFTCI;
1448 Opcode = SystemZISD::TDC;
1459 unsigned Opcode) {
1470 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1479 unsigned Opcode) {
1488 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1491 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1875 // a comparison of type Opcode between the AND result and CmpVal.
2045 C.Opcode = SystemZISD::TM;
2057 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2059 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2063 C.Opcode = Opcode;
2096 unsigned Opcode, CCValid;
2099 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2100 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2103 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2104 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2110 C.Opcode = SystemZISD::FCMP;
2114 C.Opcode = SystemZISD::ICMP;
2151 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2154 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2161 if (C.Opcode == SystemZISD::ICMP)
2164 if (C.Opcode == SystemZISD::TM) {
2170 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2190 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
2194 unsigned Extend, unsigned Opcode, SDValue Op0,
2197 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
2260 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2262 return Opcode;
2266 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2268 return Opcode;
2283 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2285 static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &DL,
2294 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2295 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2298 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2336 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2337 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2340 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2341 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2421 if (C.Opcode == SystemZISD::ICMP &&
2505 unsigned Opcode,
2543 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2992 unsigned Opcode;
2997 Opcode = SystemZISD::SDIVREM32;
3000 Opcode = SystemZISD::SDIVREM32;
3002 Opcode = SystemZISD::SDIVREM64;
3008 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
3205 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3208 unsigned Opcode) const {
3226 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3228 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3252 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3255 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3256 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3264 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3428 unsigned Opcode, CCValid;
3429 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3431 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3443 unsigned Opcode, CCValid;
3444 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3445 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3505 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3506 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3510 unsigned Opcode;
3730 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3731 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3739 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3742 } else if (P.Opcode == SystemZISD::PACK) {
3747 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
4592 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
4593 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4594 switch ((SystemZISD::NodeType)Opcode) {
4596 OPCODE(RET_FLAG);
4597 OPCODE(CALL);
4598 OPCODE(SIBCALL);
4599 OPCODE(TLS_GDCALL);
4600 OPCODE(TLS_LDCALL);
4601 OPCODE(PCREL_WRAPPER);
4602 OPCODE(PCREL_OFFSET);
4603 OPCODE(IABS);
4604 OPCODE(ICMP);
4605 OPCODE(FCMP);
4606 OPCODE(TM);
4607 OPCODE(BR_CCMASK);
4608 OPCODE(SELECT_CCMASK);
4609 OPCODE(ADJDYNALLOC);
4610 OPCODE(EXTRACT_ACCESS);
4611 OPCODE(POPCNT);
4612 OPCODE(UMUL_LOHI64);
4613 OPCODE(SDIVREM32);
4614 OPCODE(SDIVREM64);
4615 OPCODE(UDIVREM32);
4616 OPCODE(UDIVREM64);
4617 OPCODE(MVC);
4618 OPCODE(MVC_LOOP);
4619 OPCODE(NC);
4620 OPCODE(NC_LOOP);
4621 OPCODE(OC);
4622 OPCODE(OC_LOOP);
4623 OPCODE(XC);
4624 OPCODE(XC_LOOP);
4625 OPCODE(CLC);
4626 OPCODE(CLC_LOOP);
4627 OPCODE(STPCPY);
4628 OPCODE(STRCMP);
4629 OPCODE(SEARCH_STRING);
4630 OPCODE(IPM);
4631 OPCODE(SERIALIZE);
4632 OPCODE(MEMBARRIER);
4633 OPCODE(TBEGIN);
4634 OPCODE(TBEGIN_NOFLOAT);
4635 OPCODE(TEND);
4636 OPCODE(BYTE_MASK);
4637 OPCODE(ROTATE_MASK);
4638 OPCODE(REPLICATE);
4639 OPCODE(JOIN_DWORDS);
4640 OPCODE(SPLAT);
4641 OPCODE(MERGE_HIGH);
4642 OPCODE(MERGE_LOW);
4643 OPCODE(SHL_DOUBLE);
4644 OPCODE(PERMUTE_DWORDS);
4645 OPCODE(PERMUTE);
4646 OPCODE(PACK);
4647 OPCODE(PACKS_CC);
4648 OPCODE(PACKLS_CC);
4649 OPCODE(UNPACK_HIGH);
4650 OPCODE(UNPACKL_HIGH);
4651 OPCODE(UNPACK_LOW);
4652 OPCODE(UNPACKL_LOW);
4653 OPCODE(VSHL_BY_SCALAR);
4654 OPCODE(VSRL_BY_SCALAR);
4655 OPCODE(VSRA_BY_SCALAR);
4656 OPCODE(VSUM);
4657 OPCODE(VICMPE);
4658 OPCODE(VICMPH);
4659 OPCODE(VICMPHL);
4660 OPCODE(VICMPES);
4661 OPCODE(VICMPHS);
4662 OPCODE(VICMPHLS);
4663 OPCODE(VFCMPE);
4664 OPCODE(VFCMPH);
4665 OPCODE(VFCMPHE);
4666 OPCODE(VFCMPES);
4667 OPCODE(VFCMPHS);
4668 OPCODE(VFCMPHES);
4669 OPCODE(VFTCI);
4670 OPCODE(VEXTEND);
4671 OPCODE(VROUND);
4672 OPCODE(VTM);
4673 OPCODE(VFAE_CC);
4674 OPCODE(VFAEZ_CC);
4675 OPCODE(VFEE_CC);
4676 OPCODE(VFEEZ_CC);
4677 OPCODE(VFENE_CC);
4678 OPCODE(VFENEZ_CC);
4679 OPCODE(VISTR_CC);
4680 OPCODE(VSTRC_CC);
4681 OPCODE(VSTRCZ_CC);
4682 OPCODE(TDC);
4683 OPCODE(ATOMIC_SWAPW);
4684 OPCODE(ATOMIC_LOADW_ADD);
4685 OPCODE(ATOMIC_LOADW_SUB);
4686 OPCODE(ATOMIC_LOADW_AND);
4687 OPCODE(ATOMIC_LOADW_OR);
4688 OPCODE(ATOMIC_LOADW_XOR);
4689 OPCODE(ATOMIC_LOADW_NAND);
4690 OPCODE(ATOMIC_LOADW_MIN);
4691 OPCODE(ATOMIC_LOADW_MAX);
4692 OPCODE(ATOMIC_LOADW_UMIN);
4693 OPCODE(ATOMIC_LOADW_UMAX);
4694 OPCODE(ATOMIC_CMP_SWAPW);
4695 OPCODE(LRV);
4696 OPCODE(STRV);
4697 OPCODE(PREFETCH);
4700 #undef OPCODE
4725 unsigned Opcode = Op.getOpcode();
4726 if (Opcode == ISD::BITCAST)
4729 else if (Opcode == ISD::VECTOR_SHUFFLE &&
4751 } else if (Opcode == ISD::BUILD_VECTOR &&
4778 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4779 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4780 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4888 unsigned Opcode = N->getOpcode();
4903 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
4912 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
5243 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
5690 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
5705 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
5746 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
5762 if (Opcode == SystemZ::MVC)
5766 BuildMI(MBB, DL, TII->get(Opcode))
5831 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5860 // Opcode until CC != 3.
5862 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
5905 BuildMI(MBB, DL, TII->get(Opcode))
5919 // Update TBEGIN instruction with final opcode and register clobbers.
5921 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode,
5927 // Update opcode.
5928 MI.setDesc(TII->get(Opcode));
5969 MachineInstr &MI, MachineBasicBlock *MBB, unsigned Opcode) const {
5984 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
