Lines Matching refs:IdxVal
4416 static SDValue extractSubVector(SDValue Vec, unsigned IdxVal, SelectionDAG &DAG,
4436 IdxVal &= ~(ElemsPerChunk - 1);
4441 dl, ResultVT, makeArrayRef(Vec->op_begin() + IdxVal, ElemsPerChunk));
4443 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4453 static SDValue extract128BitVector(SDValue Vec, unsigned IdxVal,
4457 return extractSubVector(Vec, IdxVal, DAG, dl, 128);
4461 static SDValue extract256BitVector(SDValue Vec, unsigned IdxVal,
4464 return extractSubVector(Vec, IdxVal, DAG, dl, 256);
4467 static SDValue insertSubVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4485 IdxVal &= ~(ElemsPerChunk - 1);
4487 SDValue VecIdx = DAG.getIntPtrConstant(IdxVal, dl);
4497 static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4506 if (IdxVal == 0 && Result.getValueType().is256BitVector() &&
4544 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 128);
4547 static SDValue insert256BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
4550 return insertSubVector(Result, Vec, IdxVal, DAG, dl, 256);
4565 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
4566 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal
4574 assert(IdxVal + SubVecNumElems <= NumElems &&
4575 IdxVal % SubVecVT.getSizeInBits() == 0 &&
4579 // 1. Subvector should be inserted in the lower part (IdxVal == 0)
4581 // (IdxVal + SubVecNumElems == NumElems)
4603 if (IdxVal != 0) {
4604 SDValue ShiftBits = DAG.getConstant(IdxVal, dl, MVT::i8);
4613 unsigned ShiftRight = NumElems - SubVecNumElems - IdxVal;
4621 if (IdxVal == 0) {
4636 if (IdxVal + SubVecNumElems == NumElems) {
4639 DAG.getConstant(IdxVal, dl, MVT::i8));
4652 Mask.push_back(i >= IdxVal && i < IdxVal + SubVecNumElems ?
6951 SDValue IdxVal = DAG.getIntPtrConstant(SubVecNumElts * OpIdx, dl);
6953 Op.getOperand(OpIdx), IdxVal);
6992 SDValue IdxVal = DAG.getIntPtrConstant(NumElems/2, dl);
6994 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, IdxVal);
6997 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, ZeroVec, V2, IdxVal);
7000 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, V1, V2, IdxVal);
12402 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12413 DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));
12453 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12459 Vec = extract128BitVector(Vec, IdxVal, DAG, dl);
12465 // Find IdxVal modulo ElemsPerChunk. Since ElemsPerChunk is a power of 2
12467 IdxVal &= ElemsPerChunk - 1;
12469 DAG.getConstant(IdxVal, dl, MVT::i32));
12481 if (IdxVal == 0)
12495 if (IdxVal == 0)
12499 int Mask[4] = { static_cast<int>(IdxVal), -1, -1, -1 };
12509 if (IdxVal == 0)
12545 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12547 if (IdxVal)
12549 DAG.getConstant(IdxVal, dl, MVT::i8));
12571 unsigned IdxVal = N2C->getZExtValue();
12581 ClearMask.push_back(i == IdxVal ? i + NumElts : i);
12591 if (VT.is256BitVector() && IdxVal == 0) {
12604 SDValue V = extract128BitVector(N0, IdxVal, DAG, dl);
12610 unsigned IdxIn128 = IdxVal & (NumEltsIn128 - 1);
12616 return insert128BitVector(N0, V, IdxVal, DAG, dl);
12635 N2 = DAG.getIntPtrConstant(IdxVal, dl);
12650 if (IdxVal == 0 && (!MinSize || !MayFoldLoad(N1))) {
12662 N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);
12683 N2 = DAG.getIntPtrConstant(IdxVal, dl);
12725 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12733 return extract128BitVector(In, IdxVal, DAG, dl);
12737 return extract256BitVector(In, IdxVal, DAG, dl);
12759 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
12767 if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
12791 return insert128BitVector(Vec, SubVec, IdxVal, DAG, dl);
12794 return insert256BitVector(Vec, SubVec, IdxVal, DAG, dl);
26425 uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
26426 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
