Lines Matching refs:MOVSD
3812 case X86ISD::MOVSD:
3862 case X86ISD::MOVSD:
4966 case X86ISD::MOVSD:
6657 // the rest of the elements. This will be matched as movd/movq/movss/movsd
6673 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector.
8440 // Otherwise, use MOVSD or MOVSS.
8443 return DAG.getNode(EltVT == MVT::f32 ? X86ISD::MOVSS : X86ISD::MOVSD, DL,
8959 isShuffleFoldableLoad(V1S) ? X86ISD::MOVLPD : X86ISD::MOVSD,
12512 // UNPCKHPD the element to the lowest double word, then movsd.
20110 // constant plus a MOVSS/MOVSD instead of scalarizing it.
20130 // two shifts followed by a MOVSS/MOVSD
20136 // Otherwise, check if we can still simplify this node using a MOVSD.
20139 TargetOpcode = X86ISD::MOVSD;
20150 TargetOpcode = X86ISD::MOVSD;
20162 // Replace this node with two shifts followed by a MOVSS/MOVSD.
20170 if (TargetOpcode == X86ISD::MOVSD)
22243 case X86ISD::MOVSD: return "X86ISD::MOVSD";
25760 // partial register update stalls, this should be transformed into a MOVSD
25761 // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
31012 case X86ISD::MOVSD:
