Lines Matching refs:VSELECT
726 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
785 setOperationAction(ISD::VSELECT, VT, Custom);
808 setOperationAction(ISD::VSELECT, VT, Custom);
900 // We directly match byte blends in the backend as they match the VSELECT
902 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
1107 setOperationAction(ISD::VSELECT, VT, Custom);
1116 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
1221 setOperationAction(ISD::VSELECT, MVT::v8i1, Expand);
1222 setOperationAction(ISD::VSELECT, MVT::v16i1, Expand);
1398 setOperationAction(ISD::VSELECT, VT, Legal);
1459 setOperationAction(ISD::VSELECT, MVT::v32i16, Legal);
1460 setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);
1468 setOperationAction(ISD::VSELECT, MVT::v32i1, Expand);
1469 setOperationAction(ISD::VSELECT, MVT::v64i1, Expand);
1499 setOperationAction(ISD::VSELECT, VT, Legal);
1548 setOperationAction(ISD::VSELECT, MVT::v2i1, Expand);
1549 setOperationAction(ISD::VSELECT, MVT::v4i1, Expand);
1635 setTargetDAGCombine(ISD::VSELECT);
7592 // Compute the VSELECT mask. Note that VSELECT is really confusing in the
7614 VT, DAG.getNode(ISD::VSELECT, DL, BlendVT,
12250 /// \brief Try to lower a VSELECT instruction to a vector shuffle.
12277 // A vselect where all conditions and data are constants can be optimized into
12294 // VSELECT-matching blend, return Op, and but if we need to expand, return
12310 // AVX-512 BWI and VLX features support VSELECT with i16 elements.
14048 SDValue SelectedVal = DAG.getNode(ISD::VSELECT, DL, ExtVT, In, One, Zero);
15766 // Convert to vectors, do a VSELECT, and convert back to scalar.
15777 SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);
16044 SDValue V = DAG.getNode(ISD::VSELECT, dl, ExtVT, In, NegOne, Zero);
17215 /// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the
17223 unsigned OpcodeSelect = ISD::VSELECT;
17245 // We can't use ISD::VSELECT here because it is not always "Legal"
17247 // and vselect that can operate on byte element type require BWI
17261 /// "X86select" instead of "vselect". We just can't create the "vselect" node
20233 // On SSE41 targets we make use of the fact that VSELECT lowers
20240 DAG.getNode(ISD::VSELECT, dl, VT, Sel, V0, V1));
20244 // and VSELECT uses that in its OR(AND(V0,C),AND(V1,~C)) lowering.
20247 return DAG.getNode(ISD::VSELECT, dl, SelVT, C, V0, V1);
20250 // Turn 'a' into a mask suitable for VSELECT: a = a << 5;
20258 // r = VSELECT(r, shift(r, 4), a);
20266 // r = VSELECT(r, shift(r, 2), a);
20273 // return VSELECT
20292 // r = VSELECT(r, shift(r, 4), a);
20304 // r = VSELECT(r, shift(r, 2), a);
20316 // r = VSELECT(r, shift(r, 1), a);
20375 // On SSE41 targets we make use of the fact that VSELECT lowers
20383 VT, DAG.getNode(ISD::VSELECT, dl, ExtVT, Sel, V0, V1));
20386 // set all bits of the lanes to true and VSELECT uses that in
20390 return DAG.getNode(ISD::VSELECT, dl, VT, C, V0, V1);
20393 // Turn 'a' into a mask suitable for VSELECT: a = a << 12;
20405 // r = VSELECT(r, shift(r, 8), a);
20412 // r = VSELECT(r, shift(r, 4), a);
20419 // r = VSELECT(r, shift(r, 2), a);
20426 // return VSELECT(r, shift(r, 1), a);
21677 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
26433 /// Do target-specific dag combines on SELECT and VSELECT nodes.
26739 if (N->getOpcode() == ISD::VSELECT && Cond.getOpcode() == ISD::SETCC &&
26745 // Check if one of the arms of the VSELECT is a zero vector. If it's on the
26798 // Simplify vector selection if condition value type matches vselect
26800 if (N->getOpcode() == ISD::VSELECT && CondVT == VT) {
26850 if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
26859 // We can only handle the cases where VSELECT is directly legal on the
26860 // subtarget. We custom lower VSELECT nodes with constant conditions and
26861 // this makes it hard to see whether a dynamic VSELECT will correctly
26866 // Potentially, we should combine constant-condition vselect nodes
26869 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
26895 // use the generic VSELECT anymore. Otherwise, we may perform
26904 if (I->getOpcode() != ISD::VSELECT)
26909 VSELECT optimizations that expect the correct vector
28291 // (vselect m, x, y)
28354 // which is a special case of vselect:
28355 // (vselect M, (sub 0, X), X)
28364 // This lets us transform our vselect to:
28387 // (vselect M, (sub (0, X), X) -> (sub (xor X, M), M)
28389 // (vselect M, X, (sub (0, X))), that is really negation of the pattern
28390 // above, -(vselect M, (sub 0, X), X), and therefore the replacement
28411 Mask = DAG.getNode(ISD::VSELECT, DL, BlendVT, Mask, Y, X);
29892 auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
30665 if (Op0.getOpcode() == ISD::VSELECT) {
30668 } else if (Op1.getOpcode() == ISD::VSELECT) {
30951 case ISD::VSELECT:
