Lines Matching refs:RecVec
139 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
179 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
186 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
192 RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
195 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
212 RecVec SWDefs, SRDefs;
217 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
228 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
231 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
243 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
246 RecVec RWDefs = (*II)->getValueAsListOfDefs("OperandReadWrites");
259 RecVec AliasDefs = Records.getAllDerivedDefinitions("SchedAlias");
317 RecVec RWDefs = Records.getAllDerivedDefinitions("SchedReadWrite");
358 RecVec ValidWrites = ReadDef->getValueAsListOfDefs("ValidWrites");
368 void splitSchedReadWrites(const RecVec &RWDefs,
369 RecVec &WriteDefs, RecVec &ReadDefs) {
382 void CodeGenSchedModels::findRWs(const RecVec &RWDefs,
384 RecVec WriteDefs;
385 RecVec ReadDefs;
392 void CodeGenSchedModels::findRWs(const RecVec &RWDefs, IdxVec &RWs,
520 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
560 const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs;
627 std::string CodeGenSchedModels::createSchedClassName(const RecVec &InstDefs) {
679 const RecVec *InstDefs = Sets.expand(InstRWDef);
708 const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs;
710 const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]);
782 RecVec ItinRecords = ProcModel.ItinsDef->getValueAsListOfDefs("IID");
821 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW");
876 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
897 const RecVec *InstDefs = Sets.expand(Rec);
993 RecVec Variants = SchedRW.TheDef->getValueAsListOfDefs("Variants");
1071 const RecVec VarDefs = SchedRW.TheDef->getValueAsListOfDefs("Variants");
1091 const RecVec VarDefs = AliasRW.TheDef->getValueAsListOfDefs("Variants");
1160 RecVec SelectedDefs = VInfo.VarOrSeqDef->getValueAsListOfDefs("Selected");
1321 RecVec Preds;
1395 bool CodeGenSchedModels::hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM) {
1399 RecVec SuperUnits =
1419 RecVec CheckUnits =
1424 RecVec OtherUnits =
1473 RecVec WRDefs = Records.getAllDerivedDefinitions("WriteRes");
1478 RecVec SWRDefs = Records.getAllDerivedDefinitions("SchedWriteRes");
1483 RecVec RADefs = Records.getAllDerivedDefinitions("ReadAdvance");
1488 RecVec SRADefs = Records.getAllDerivedDefinitions("SchedReadAdvance");
1497 RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup");
1574 const RecVec &InstRWs = SC.InstRWs;
1609 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
1743 RecVec &WRDefs = ProcModels[PIdx].WriteResDefs;
1750 RecVec ProcResDefs = ProcWriteResDef->getValueAsListOfDefs("ProcResources");
1760 RecVec &RADefs = ProcModels[PIdx].ReadAdvanceDefs;
