Lines Matching refs:rtex
40 struct r600_texture *rtex);
182 struct r600_texture *rtex, unsigned level,
188 *stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe;
189 *layer_stride = rtex->surface.u.gfx9.surf_slice_size;
196 return box->z * rtex->surface.u.gfx9.surf_slice_size +
197 rtex->surface.u.gfx9.offset[level] +
198 (box->y / rtex->surface.blk_h *
199 rtex->surface.u.gfx9.surf_pitch +
200 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
202 *stride = rtex->surface.u.legacy.level[level].nblk_x *
203 rtex->surface.bpe;
204 assert((uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 <= UINT_MAX);
205 *layer_stride = (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4;
208 return rtex->surface.u.legacy.level[level].offset;
212 return rtex->surface.u.legacy.level[level].offset +
213 box->z * (uint64_t)rtex->surface.u.legacy.level[level].slice_size_dw * 4 +
214 (box->y / rtex->surface.blk_h *
215 rtex->surface.u.legacy.level[level].nblk_x +
216 box->x / rtex->surface.blk_w) * rtex->surface.bpe;
325 struct r600_texture *rtex,
328 struct radeon_surf *surface = &rtex->surface;
386 struct r600_texture *rtex)
394 ctx->flush_resource(ctx, &rtex->resource.b.b);
402 struct r600_texture *rtex)
404 if (!rtex->cmask.size)
407 assert(rtex->resource.b.b.nr_samples <= 1);
410 memset(&rtex->cmask, 0, sizeof(rtex->cmask));
411 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
412 rtex->dirty_level_mask = 0;
414 rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
416 if (rtex->cmask_buffer != &rtex->resource)
417 r600_resource_reference(&rtex->cmask_buffer, NULL);
424 static bool r600_can_disable_dcc(struct r600_texture *rtex)
427 return rtex->dcc_offset &&
428 (!rtex->resource.b.is_shared ||
429 !(rtex->resource.external_usage & PIPE_HANDLE_USAGE_WRITE));
433 struct r600_texture *rtex)
435 if (!r600_can_disable_dcc(rtex))
438 assert(rtex->dcc_separate_buffer == NULL);
441 rtex->dcc_offset = 0;
470 struct r600_texture *rtex)
474 if (!r600_can_disable_dcc(rtex))
481 rctx->decompress_dcc(&rctx->b, rtex);
487 return r600_texture_discard_dcc(sscreen, rtex);
491 struct r600_texture *rtex,
497 struct pipe_resource templ = rtex->resource.b.b;
502 if (rtex->resource.b.is_shared)
506 if (rtex->surface.is_linear)
529 &rtex->resource.b.b, i, &box);
534 r600_texture_discard_cmask(rctx->screen, rtex);
535 r600_texture_discard_dcc(rctx->screen, rtex);
538 /* Replace the structure fields of rtex. */
539 rtex->resource.b.b.bind = templ.bind;
540 pb_reference(&rtex->resource.buf, new_tex->resource.buf);
541 rtex->resource.gpu_address = new_tex->resource.gpu_address;
542 rtex->resource.vram_usage = new_tex->resource.vram_usage;
543 rtex->resource.gart_usage = new_tex->resource.gart_usage;
544 rtex->resource.bo_size = new_tex->resource.bo_size;
545 rtex->resource.bo_alignment = new_tex->resource.bo_alignment;
546 rtex->resource.domains = new_tex->resource.domains;
547 rtex->resource.flags = new_tex->resource.flags;
548 rtex->size = new_tex->size;
549 rtex->db_render_format = new_tex->db_render_format;
550 rtex->db_compatible = new_tex->db_compatible;
551 rtex->can_sample_z = new_tex->can_sample_z;
552 rtex->can_sample_s = new_tex->can_sample_s;
553 rtex->surface = new_tex->surface;
554 rtex->fmask = new_tex->fmask;
555 rtex->cmask = new_tex->cmask;
556 rtex->cb_color_info = new_tex->cb_color_info;
557 rtex->last_msaa_resolve_target_micro_mode = new_tex->last_msaa_resolve_target_micro_mode;
558 rtex->htile_offset = new_tex->htile_offset;
559 rtex->tc_compatible_htile = new_tex->tc_compatible_htile;
560 rtex->depth_cleared = new_tex->depth_cleared;
561 rtex->stencil_cleared = new_tex->stencil_cleared;
562 rtex->dcc_gather_statistics = new_tex->dcc_gather_statistics;
563 rtex->framebuffers_bound = new_tex->framebuffers_bound;
566 assert(!rtex->htile_offset);
567 assert(!rtex->cmask.size);
568 assert(!rtex->fmask.size);
569 assert(!rtex->dcc_offset);
570 assert(!rtex->is_depth);
584 struct r600_texture *rtex,
587 struct pipe_resource *res = &rtex->resource.b.b;
601 assert(rtex->dcc_separate_buffer == NULL);
602 assert(rtex->fmask.size == 0);
619 si_make_texture_descriptor(sscreen, rtex, true,
626 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
627 0, 0, rtex->surface.blk_w, false, desc);
632 desc[7] = rtex->dcc_offset >> 8;
641 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
648 struct r600_texture *rtex,
663 rtex->dcc_offset = (uint64_t)desc[7] << 8;
670 rtex->dcc_offset = 0;
682 struct r600_texture *rtex = (struct r600_texture*)resource;
695 if (resource->nr_samples > 1 || rtex->is_depth)
700 rtex->surface.tile_swizzle ||
701 (rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING &&
704 r600_reallocate_texture_inplace(rctx, rtex,
710 assert(rtex->surface.tile_swizzle == 0);
717 if (usage & PIPE_HANDLE_USAGE_WRITE && rtex->dcc_offset) {
718 if (si_texture_disable_dcc(rctx, rtex)) {
726 (rtex->cmask.size || rtex->dcc_offset)) {
728 r600_eliminate_fast_color_clear(rctx, rtex);
735 if (rtex->cmask.size)
736 r600_texture_discard_cmask(sscreen, rtex);
741 r600_texture_init_metadata(sscreen, rtex, &metadata);
742 si_query_opaque_metadata(sscreen, rtex, &metadata);
748 offset = rtex->surface.u.gfx9.surf_offset;
749 stride = rtex->surface.u.gfx9.surf_pitch *
750 rtex->surface.bpe;
751 slice_size = rtex->surface.u.gfx9.surf_slice_size;
753 offset = rtex->surface.u.legacy.level[0].offset;
754 stride = rtex->surface.u.legacy.level[0].nblk_x *
755 rtex->surface.bpe;
756 slice_size = (uint64_t)rtex->surface.u.legacy.level[0].slice_size_dw * 4;
763 rtex->resource.flags & RADEON_FLAG_NO_INTERPROCESS_SHARING) {
817 struct r600_texture *rtex = (struct r600_texture*)ptex;
818 struct r600_resource *resource = &rtex->resource;
820 r600_texture_reference(&rtex->flushed_depth_texture, NULL);
822 if (rtex->cmask_buffer != &rtex->resource) {
823 r600_resource_reference(&rtex->cmask_buffer, NULL);
826 r600_resource_reference(&rtex->dcc_separate_buffer, NULL);
827 r600_resource_reference(&rtex->last_dcc_separate_buffer, NULL);
828 FREE(rtex);
835 struct r600_texture *rtex,
840 struct pipe_resource templ = rtex->resource.b.b;
847 out->alignment = rtex->surface.u.gfx9.fmask_alignment;
848 out->size = rtex->surface.u.gfx9.fmask_size;
853 flags = rtex->surface.flags | RADEON_SURF_FMASK;
889 struct r600_texture *rtex)
891 si_texture_get_fmask_info(sscreen, rtex,
892 rtex->resource.b.b.nr_samples, &rtex->fmask);
894 rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
895 rtex->size = rtex->fmask.offset + rtex->fmask.size;
899 struct r600_texture *rtex,
907 out->alignment = rtex->surface.u.gfx9.cmask_alignment;
908 out->size = rtex->surface.u.gfx9.cmask_size;
936 unsigned width = align(rtex->resource.b.b.width0, cl_width*8);
937 unsigned height = align(rtex->resource.b.b.height0, cl_height*8);
948 out->size = util_num_layers(&rtex->resource.b.b, 0) *
953 struct r600_texture *rtex)
955 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
957 rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
958 rtex->size = rtex->cmask.offset + rtex->cmask.size;
960 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
964 struct r600_texture *rtex)
972 rtex->surface.htile_size = 0;
976 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
1016 width = align(rtex->resource.b.b.width0, cl_width * 8);
1017 height = align(rtex->resource.b.b.height0, cl_height * 8);
1025 rtex->surface.htile_alignment = base_align;
1026 rtex->surface.htile_size =
1027 util_num_layers(&rtex->resource.b.b, 0) *
1032 struct r600_texture *rtex)
1034 if (sscreen->info.chip_class <= VI && !rtex
1035 r600_texture_get_htile_size(sscreen, rtex);
1037 if (!rtex->surface.htile_size)
1040 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment);
1041 rtex->size = rtex->htile_offset + rtex->surface.htile_size;
1045 struct r600_texture *rtex, struct u_log_context *log)
1053 rtex->resource.b.b.width0, rtex->resource.b.b.height0,
1054 rtex->resource.b.b.depth0, rtex->surface.blk_w,
1055 rtex->surface.blk_h,
1056 rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
1057 rtex->surface.bpe, rtex->resource.b.b.nr_samples,
1058 rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
1063 rtex->surface.surf_size,
1064 rtex->surface.u.gfx9.surf_slice_size,
1065 rtex->surface.surf_alignment,
1066 rtex->surface.u.gfx9.surf.swizzle_mode,
1067 rtex->surface.u.gfx9.surf.epitch,
1068 rtex->surface.u.gfx9.surf_pitch);
1070 if (rtex->fmask.size) {
1073 rtex->fmask.offset,
1074 rtex->surface.u.gfx9.fmask_size,
1075 rtex->surface.u.gfx9.fmask_alignment,
1076 rtex->surface.u.gfx9.fmask.swizzle_mode,
1077 rtex->surface.u.gfx9.fmask.epitch);
1080 if (rtex->cmask.size) {
1083 rtex->cmask.offset,
1084 rtex->surface.u.gfx9.cmask_size,
1085 rtex->surface.u.gfx9.cmask_alignment,
1086 rtex->surface.u.gfx9.cmask.rb_aligned,
1087 rtex->surface.u.gfx9.cmask.pipe_aligned);
1090 if (rtex->htile_offset) {
1093 rtex->htile_offset,
1094 rtex->surface.htile_size,
1095 rtex->surface.htile_alignment,
1096 rtex->surface.u.gfx9.htile.rb_aligned,
1097 rtex->surface.u.gfx9.htile.pipe_aligned);
1100 if (rtex->dcc_offset) {
1103 rtex->dcc_offset, rtex->surface.dcc_size,
1104 rtex->surface.dcc_alignment,
1105 rtex->surface.u.gfx9.dcc_pitch_max,
1106 rtex->surface.num_dcc_levels);
1109 if (rtex->surface.u.gfx9.stencil_offset) {
1111 rtex->surface.u.gfx9.stencil_offset,
1112 rtex->surface.u.gfx9.stencil.swizzle_mode,
1113 rtex->surface.u.gfx9.stencil.epitch);
1120 rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
1121 rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
1122 rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
1123 (rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
1125 if (rtex->fmask.size)
1128 rtex->fmask.offset, rtex->fmask.size, rtex->fmask.alignment,
1129 rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
1130 rtex->fmask.slice_tile_max, rtex->fmask.tile_mode_index);
1132 if (rtex->cmask.size)
1135 rtex->cmask.offset, rtex->cmask.size, rtex->cmask.alignment,
1136 rtex->cmask.slice_tile_max);
1138 if (rtex->htile_offset)
1141 rtex->htile_offset, rtex->surface.htile_size,
1142 rtex->surface.htile_alignment,
1143 rtex->tc_compatible_htile);
1145 if (rtex->dcc_offset) {
1147 rtex->dcc_offset, rtex->surface.dcc_size,
1148 rtex->surface.dcc_alignment);
1149 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
1152 i, i < rtex->surface.num_dcc_levels,
1153 rtex->surface.u.legacy.level[i].dcc_offset,
1154 rtex->surface.u.legacy.level[i].dcc_fast_clear_size);
1157 for (i = 0; i <= rtex->resource.b.b.last_level; i++)
1161 i, rtex->surface.u.legacy.level[i].offset,
1162 (uint64_t)rtex->surface.u.legacy.level[i].slice_size_dw * 4,
1163 u_minify(rtex->resource.b.b.width0, i),
1164 u_minify(rtex->resource.b.b.height0, i),
1165 u_minify(rtex->resource.b.b.depth0, i),
1166 rtex->surface.u.legacy.level[i].nblk_x,
1167 rtex->surface.u.legacy.level[i].nblk_y,
1168 rtex->surface.u.legacy.level[i].mode,
1169 rtex->surface.u.legacy.tiling_index[i]);
1171 if (rtex->surface.has_stencil) {
1173 rtex->surface.u.legacy.stencil_tile_split);
1174 for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
1179 i, rtex->surface.u.legacy.stencil_level[i].offset,
1180 (uint64_t)rtex->surface.u.legacy.stencil_level[i].slice_size_dw * 4,
1181 u_minify(rtex->resource.b.b.width0, i),
1182 u_minify(rtex->resource.b.b.height0, i),
1183 u_minify(rtex->resource.b.b.depth0, i),
1184 rtex->surface.u.legacy.stencil_level[i].nblk_x,
1185 rtex->surface.u.legacy.stencil_level[i].nblk_y,
1186 rtex->surface.u.legacy.stencil_level[i].mode,
1187 rtex->surface.u.legacy.stencil_tiling_index[i]);
1199 struct r600_texture *rtex;
1203 rtex = CALLOC_STRUCT(r600_texture);
1204 if (!rtex)
1207 resource = &rtex->resource;
1215 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format));
1217 rtex->surface = *surface;
1218 rtex->size = rtex->surface.surf_size;
1220 rtex->tc_compatible_htile = rtex->surface.htile_size != 0 &&
1221 (rtex->surface.flags &
1227 if (rtex->tc_compatible_htile) {
1230 rtex->db_render_format = base->format;
1232 rtex->db_render_format = PIPE_FORMAT_Z32_FLOAT;
1233 rtex->upgraded_depth = base->format != PIPE_FORMAT_Z32_FLOAT &&
1237 rtex->db_render_format = base->format;
1241 rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
1247 rtex->ps_draw_ratio = 0;
1249 if (rtex->is_depth) {
1251 rtex->can_sample_z = true;
1252 rtex->can_sample_s = true;
1254 rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
1255 rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
1260 rtex->db_compatible = true;
1263 r600_texture_allocate_htile(sscreen, rtex);
1268 r600_texture_allocate_fmask(sscreen, rtex);
1269 r600_texture_allocate_cmask(sscreen, rtex);
1270 rtex->cmask_buffer = &rtex->resource;
1272 if (!rtex->fmask.size || !rtex->cmask.size) {
1273 FREE(rtex);
1282 if (rtex->surface.dcc_size &&
1284 !(rtex->surface.flags & RADEON_SURF_SCANOUT)) {
1286 rtex->dcc_offset = align64(rtex->size, rtex->surface.dcc_alignment);
1287 rtex->size = rtex->dcc_offset + rtex->surface.dcc_size;
1293 si_init_resource_fields(sscreen, resource, rtex->size,
1294 rtex->surface.surf_alignment);
1297 FREE(rtex);
1312 if (rtex->cmask.size) {
1314 si_screen_clear_buffer(sscreen, &rtex->cmask_buffer->b.b,
1315 rtex->cmask.offset, rtex->cmask.size,
1318 if (rtex->htile_offset) {
1321 if (sscreen->info.chip_class >= GFX9 || rtex->tc_compatible_htile)
1324 si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
1325 rtex->htile_offset,
1326 rtex->surface.htile_size,
1331 if (!buf && rtex->dcc_offset) {
1332 si_screen_clear_buffer(sscreen, &rtex->resource.b.b,
1333 rtex->dcc_offset,
1334 rtex->surface.dcc_size,
1339 rtex->cmask.base_address_reg =
1340 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1344 rtex->resource.gpu_address,
1345 rtex->resource.gpu_address + rtex->resource.buf->size,
1354 si_print_texture_info(sscreen, rtex, &log);
1360 return rtex;
1472 struct r600_texture *rtex;
1494 rtex = r600_texture_create_object(screen, templ, buf, &surface);
1495 if (!rtex)
1498 rtex->resource.b.is_shared = true;
1499 rtex->resource.external_usage = usage;
1501 si_apply_opaque_metadata(sscreen, rtex, &metadata);
1503 assert(rtex->surface.tile_swizzle == 0);
1504 return &rtex->resource.b.b;
1511 struct r600_texture *rtex
1514 staging : &rtex->flushed_depth_texture;
1518 if (rtex->flushed_depth_texture)
1521 if (!rtex->can_sample_z && rtex->can_sample_s) {
1542 } else if (!rtex->can_sample_s && rtex->can_sample_z) {
1603 struct r600_texture *rtex,
1607 return !rtex->resource.b.is_shared &&
1609 rtex->resource.b.b.last_level == 0 &&
1610 util_texrange_covers_whole_level(&rtex->resource.b.b, 0,
1617 struct r600_texture *rtex)
1622 assert(!rtex->is_depth);
1623 assert(rtex->surface.is_linear);
1626 si_alloc_resource(sscreen, &rtex->resource);
1629 rtex->cmask.base_address_reg =
1630 (rtex->resource.gpu_address + rtex->cmask.offset) >> 8;
1634 rctx->num_alloc_tex_transfer_bytes += rtex->size;
1645 struct r600_texture *rtex = (struct r600_texture*)texture;
1656 if (!rtex->is_depth) {
1664 p_atomic_inc_return(&rtex->num_level0_transfers) == 10) {
1666 r600_can_invalidate_texture(rctx->screen, rtex,
1669 r600_reallocate_texture_inplace(rctx, rtex,
1683 if (!rtex->surface.is_linear)
1687 rtex->resource.domains & RADEON_DOMAIN_VRAM ||
1688 rtex->resource.flags & RADEON_FLAG_GTT_WC;
1690 else if (si_rings_is_buffer_referenced(rctx, rtex->resource.buf,
1692 !rctx->ws->buffer_wait(rtex->resource.buf, 0,
1695 if (r600_can_invalidate_texture(rctx->screen, rtex,
1697 r600_texture_invalidate_storage(rctx, rtex);
1711 if (rtex->is_depth) {
1714 if (rtex->resource.b.b.nr_samples > 1) {
1762 rctx->blit_decompress_depth(ctx, rtex, staging_depth,
1806 offset = r600_texture_get_offset(rctx->screen, rtex, level, box,
1809 buf = &rtex->resource;
1828 struct r600_texture *rtex = (struct r600_texture*)texture;
1831 if (rtex->is_depth && rtex->resource.b.b.nr_samples <= 1) {
1965 struct r600_texture *rtex = (struct r600_texture *)tex;
1967 return vi_dcc_enabled(rtex, level) &&
1978 struct r600_texture *rtex = (struct r600_texture *)tex;
1982 rctx->decompress_dcc(&rctx->b, rtex);
2408 struct r600_texture *rtex;
2454 rtex = r600_texture_create_object(screen, templ, memobj->buf, &surface);
2455 if (!rtex)
2463 rtex->resource.b.is_shared = true;
2464 rtex->resource.external_usage = PIPE_HANDLE_USAGE_READ_WRITE;
2466 si_apply_opaque_metadata(sscreen, rtex, &metadata);
2468 return &rtex->resource.b.b;
