Lines Matching refs:rtex
37 struct r600_texture *rtex)
39 if (rtex->cmask_buffer)
42 assert(rtex->cmask.size == 0);
44 si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
45 if (!rtex->cmask.size)
48 rtex->cmask_buffer = (struct r600_resource *)
52 rtex->cmask.size,
53 rtex->cmask.alignment);
54 if (rtex->cmask_buffer == NULL) {
55 rtex->cmask.size = 0;
60 rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
62 rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
67 static void si_set_clear_color(struct r600_texture *rtex,
75 if (rtex->surface.bpe == 16) {
92 memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
194 struct r600_texture *rtex,
200 assert(vi_dcc_enabled(rtex, level));
202 if (rtex->dcc_separate_buffer) {
203 dcc_buffer = &rtex->dcc_separate_buffer->b.b;
206 dcc_buffer = &rtex->resource.b.b;
207 dcc_offset = rtex->dcc_offset;
212 assert(rtex->resource.b.b.last_level == 0);
214 assert(rtex->resource.b.b.nr_samples <= 1);
215 clear_size = rtex->surface.dcc_size;
217 unsigned num_layers = util_num_layers(&rtex->resource.b.b, level);
220 assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
225 assert(rtex->resource.b.b.nr_samples <= 1 || num_layers == 1);
227 dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
228 clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
241 struct r600_texture *rtex)
243 if (rtex->resource.b.is_shared ||
244 rtex->resource.b.b.nr_samples <= 1 ||
245 rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
249 rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
250 assert(rtex->resource.b.b.last_level == 0);
254 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
264 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
266 switch (rtex->last_msaa_resolve_target_micro_mode) {
268 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
269 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
272 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
273 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
276 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
277 rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
288 switch (rtex->last_msaa_resolve_target_micro_mode) {
290 rtex->surface.u.legacy.tiling_index[0] = 10;
293 rtex->surface.u.legacy.tiling_index[0] = 14;
296 rtex->surface.u.legacy.tiling_index[0] = 28;
303 switch (rtex->last_msaa_resolve_target_micro_mode) {
305 switch (rtex->surface.bpe) {
307 rtex->surface.u.legacy.tiling_index[0] = 10;
310 rtex->surface.u.legacy.tiling_index[0] = 11;
313 rtex->surface.u.legacy.tiling_index[0] = 12;
318 switch (rtex->surface.bpe) {
320 rtex->surface.u.legacy.tiling_index[0] = 14;
323 rtex->surface.u.legacy.tiling_index[0] = 15;
326 rtex->surface.u.legacy.tiling_index[0] = 16;
329 rtex->surface.u.legacy.tiling_index[0] = 17;
339 rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
669 struct r600_texture *rtex = (struct r600_texture*)tex;
683 if (rtex->is_depth) {
692 if (rtex->surface.has_stencil) {
