Lines Matching refs:sctx
108 struct si_context *sctx = (struct si_context *)context;
118 si_release_all_descriptors(sctx);
120 pipe_resource_reference(&sctx->esgs_ring, NULL);
121 pipe_resource_reference(&sctx->gsvs_ring, NULL);
122 pipe_resource_reference(&sctx->tf_ring, NULL);
123 pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
124 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
125 r600_resource_reference(&sctx->border_color_buffer, NULL);
126 free(sctx->border_color_table);
127 r600_resource_reference(&sctx->scratch_buffer, NULL);
128 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
129 r600_resource_reference(&sctx->wait_mem_scratch, NULL);
131 si_pm4_free_state(sctx, sctx->init_config, ~0);
132 if (sctx->init_config_gs_rings)
133 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
134 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
135 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
137 if (sctx->fixed_func_tcs_shader.cso)
138 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
139 if (sctx->custom_dsa_flush)
140 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
141 if (sctx->custom_blend_resolve)
142 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
143 if (sctx->custom_blend_fmask_decompress)
144 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fmask_decompress);
145 if (sctx->custom_blend_eliminate_fastclear)
146 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_eliminate_fastclear);
147 if (sctx->custom_blend_dcc_decompress)
148 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
149 if (sctx->vs_blit_pos)
150 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos);
151 if (sctx->vs_blit_pos_layered)
152 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_pos_layered);
153 if (sctx->vs_blit_color)
154 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color);
155 if (sctx->vs_blit_color_layered)
156 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_color_layered);
157 if (sctx->vs_blit_texcoord)
158 sctx->b.b.delete_vs_state(&sctx->b.b, sctx->vs_blit_texcoord);
160 if (sctx->blitter)
161 util_blitter_destroy(sctx->blitter);
163 si_common_context_cleanup(&sctx->b);
165 LLVMDisposeTargetMachine(sctx->tm);
167 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
169 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
170 _mesa_hash_table_destroy(sctx->img_handles, NULL);
172 util_dynarray_fini(&sctx->resident_tex_handles);
173 util_dynarray_fini(&sctx->resident_img_handles);
174 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
175 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
176 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
177 FREE(sctx);
183 struct si_context *sctx = (struct si_context *)ctx;
185 return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
199 struct si_context *sctx = (struct si_context *)ctx;
201 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
203 if (sctx->b.log)
204 u_log_printf(sctx->b.log, "\nString marker: %*s\n", len, string);
222 struct si_context *sctx = (struct si_context *)ctx;
223 struct si_screen *screen = sctx->screen;
229 sctx->debug = *cb;
231 memset(&sctx->debug, 0, sizeof(sctx->debug));
237 struct si_context *sctx = (struct si_context *)ctx;
238 sctx->b.log = log;
241 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
247 struct si_context *sctx = CALLOC_STRUCT(si_context);
252 if (!sctx)
258 sctx->b.b.screen = screen; /* this must be set first */
259 sctx->b.b.priv = NULL;
260 sctx->b.b.destroy = si_destroy_context;
261 sctx->b.b.emit_string_marker = si_emit_string_marker;
262 sctx->b.b.set_debug_callback = si_set_debug_callback;
263 sctx->b.b.set_log_context = si_set_log_context;
264 sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
265 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
266 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
268 if (!si_common_context_init(&sctx->b, sscreen, flags))
272 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
274 si_init_buffer_functions(sctx);
275 si_init_clear_functions(sctx);
276 si_init_blit_functions(sctx);
277 si_init_compute_functions(sctx);
278 si_init_cp_dma_functions(sctx);
279 si_init_debug_functions(sctx);
280 si_init_msaa_functions(sctx);
281 si_init_streamout_functions(sctx);
284 sctx->b.b.create_video_codec = si_uvd_create_decoder;
285 sctx->b.b.create_video_buffer = si_video_buffer_create;
287 sctx->b.b.create_video_codec = vl_create_decoder;
288 sctx->b.b.create_video_buffer = vl_video_buffer_create;
291 sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
292 si_context_gfx_flush, sctx);
293 sctx->b.gfx.flush = si_context_gfx_flush;
296 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
297 sizeof(*sctx->border_color_table));
298 if (!sctx->border_color_table)
301 sctx->border_color_buffer = (struct r600_resource*)
304 sizeof(*sctx->border_color_table));
305 if (!sctx->border_color_buffer)
308 sctx->border_color_map =
309 ws->buffer_map(sctx->border_color_buffer->buf,
311 if (!sctx->border_color_map)
314 si_init_all_descriptors(sctx);
315 si_init_fence_functions(sctx);
316 si_init_state_functions(sctx);
317 si_init_shader_functions(sctx);
318 si_init_viewport_functions(sctx);
319 si_init_ia_multi_vgt_param_table(sctx);
321 if (sctx->b.chip_class >= CIK)
322 cik_init_sdma_functions(sctx);
324 si_init_dma_functions(sctx);
327 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
329 sctx->blitter = util_blitter_create(&sctx->b.b);
330 if (sctx->blitter == NULL)
332 sctx->blitter->draw_rectangle = si_draw_rectangle;
333 sctx->blitter->skip_viewport_restore = true;
335 sctx->sample_mask.sample_mask = 0xffff;
337 if (sctx->b.chip_class >= GFX9) {
338 sctx->wait_mem_scratch = (struct r600_resource*)
340 if (!sctx->wait_mem_scratch)
344 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
349 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address);
350 radeon_emit(cs, sctx->wait_mem_scratch->gpu_address >> 32);
351 radeon_emit(cs, sctx->wait_mem_number);
352 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
353 sctx->wait_mem_scratch,
359 if (sctx->b.chip_class == CIK) {
360 sctx->null_const_buf.buffer =
364 sctx->screen->info.tcc_cache_line_size);
365 if (!sctx->null_const_buf.buffer)
367 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
371 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
372 &sctx->null_const_buf);
376 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
377 &sctx->null_const_buf);
378 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
379 &sctx->null_const_buf);
380 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
381 &sctx->null_const_buf);
382 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
383 &sctx->null_const_buf);
384 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
385 &sctx->null_const_buf);
388 si_clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
389 sctx->null_const_buf.buffer->width0, 0,
402 * sctx->scratch_waves must be >= the maximum posible size of
410 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
413 sctx->tm = si_create_llvm_target_machine(sscreen);
416 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
418 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
421 util_dynarray_init(&sctx->resident_tex_handles, NULL);
422 util_dynarray_init(&sctx->resident_img_handles, NULL);
423 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
424 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
425 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
428 si_begin_new_cs(sctx);
429 return &sctx->b.b;
432 sctx->b.b);
593 struct si_context *sctx = (struct si_context *)ctx;
605 si_copy_buffer(sctx, buf, buf, 0, 4, 4, 0);
610 sctx->b.dma_clear_buffer(ctx, buf, 0, 4, 0);
