Lines Matching refs:pm4
472 struct si_pm4_state *pm4 = &blend->pm4;
490 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
538 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
548 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
612 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
645 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
654 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
861 struct si_pm4_state *pm4 = &rs->pm4;
897 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
908 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
921 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
925 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
927 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
935 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
939 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
940 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
964 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
989 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
991 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
993 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
995 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
997 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1179 struct si_pm4_state *pm4 = &dsa->pm4;
1218 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1224 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1226 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1228 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1229 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
4605 struct si_pm4_state *pm4, unsigned value)
4609 si_pm4_set_reg(pm4, reg, value);
4613 struct si_pm4_state *pm4, unsigned se)
4616 si_set_grbm_gfx_index(sctx, pm4,
4625 struct si_pm4_state *pm4,
4725 si_set_grbm_gfx_index_se(sctx, pm4, se);
4726 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4728 si_set_grbm_gfx_index(sctx, pm4, ~0);
4744 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4748 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4837 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4840 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4843 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4852 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4857 if (!pm4)
4860 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4861 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4862 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4863 si_pm4_cmd_end(pm4, false);
4866 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4867 si_pm4_cmd_add(pm4, 0);
4868 si_pm4_cmd_end(pm4, false);
4872 si_set_raster_config(sctx, pm4);
4874 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4876 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4880 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4881 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4885 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4886 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4887 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4890 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4892 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4894 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4897 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4898 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4901 si_pm4_set_reg(pm4
4907 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4908 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4909 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4910 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4912 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4913 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4918 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4919 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4929 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4930 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4931 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4932 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4933 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4934 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4938 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4939 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4940 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4946 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4947 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4948 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4953 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4956 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4958 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4960 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4967 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4971 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5003 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5006 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5008 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5028 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5030 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5031 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5034 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5036 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
5037 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5055 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5058 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5060 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5063 si_pm4_upload_indirect_buffer(sctx, pm4);
5064 sctx->init_config = pm4;
